cnt60.vhd.bak

基于VHDL的电子钟 实现一个简单的电子钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt60 is
port(  	ch,cl : buffer std_logic_vector (3 downto 0);
      	clk : in std_logic ;
		carry: buffer std_logic   --?? buffer
	);  
end cnt60;
architecture cnt60_display of cnt60 is
begin
  process(clk)

  begin 

	if clk'event and clk='1' then
	  if cl=9 then
	  	if ch=5 then
		   ch <="0000"; cl <= "0000" ; 
		carry <= not carry ;
		else cl <= "0000"; ch <= ch+1;
					carry <= '0';
		end if;
	  else cl <= cl +1 ;	carry <= '0';
	  end if;
	end if;
  end process;
end cnt60_display;