leddrv.vhd

数字时钟vhdl实现

--/*****************************************************************************
-- * 源文件:	leddrv.vhd
-- * 模块:   	LED驱动
-- * 版权:
-- *         	Copyright(C) 北京联华众科科技有限公司
-- *						www.lianhua-zhongke.com.cn
-- * 版本：  	Version 1.0
-- * 
-- * 功能说明:
-- *		   	将输入的4位二进制数转为8位可驱动LED的二进制位。
-- * 参数说明：
-- *	       	输出参数
-- *			led_bits - 8位可驱动LED的二进制位
-- *
-- *			输入参数
-- *			data - 4位二进制数
-- *			reset - 复位信号，低电平有效
-- *
-- *			参数
-- *
-- * 变更记录: 
-- *         2006.01.28, 新建
-- *
-- *****************************************************************************/

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY leddrv IS
	PORT
	(
		data : IN STD_LOGIC_VECTOR(3 downto 0);
		reset : IN STD_LOGIC;
		led_bits : OUT STD_LOGIC_VECTOR(7 downto 0)
	);
END leddrv;

ARCHITECTURE leddrv_architecture OF leddrv IS
BEGIN
	PROCESS(data, reset)
	BEGIN		

		IF (reset = '0') THEN
			led_bits <= "11111111";
		ELSE
			CASE data IS
				WHEN "0000" => led_bits <= "11111111";
				WHEN "0001" => led_bits <= "11111110";
				WHEN "0010" => led_bits <= "11111101";
				WHEN "0011" => led_bits <= "11111011";
				WHEN "0100" => led_bits <= "11110111";
				WHEN "0101" => led_bits <= "11101111";
				WHEN "0110" => led_bits <= "11011111";
				WHEN "0111" => led_bits <= "10111111";
				WHEN "1000" => led_bits <= "01111111";
				WHEN "1001" => led_bits <= "00000000";
				WHEN OTHERS => led_bits <= "11111111";
			END CASE;
		END IF;
	END PROCESS;
	
END leddrv_architecture;