sync_s.v

包含了四位计数器等基本数字模块的的verilog HDL程序代码,该功能实现,可以直接利用DC进行综合,得到硬件电路,亦能够转换成VHDL语言进行综合

//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.34  Oct. 7, 2003 
// Wed Mar 10 16:54:51 2004
//
//      Input file         : /home/mcgett/temp/paulg/vhdl/sync.vhd
//      Design name        : SYNC
//      Author             : 
//      Company            : 
//
//      Description        : 
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
//
// Sychronizer circuit, and read control, as well as stall generation. Assumes that read port
// cannot keep up with the write circuit, and hence generates a stall signal that disables the
// write port.  The source of the data must stop inputing data until the stall goes away.
// Signalling between the read and write circuits is double buffered to prevent metastability.
//
module SYNC (RESET, RD_CLK, WR_CLK, DECREMENT_BCOUNT, INCREMENT_BCOUNT, ENABLE_IN, WRITE_ENABLE, READ_ENABLE);

`include "parameter_file.v"

   input RESET; 
   input RD_CLK; 
   input WR_CLK; 
   input DECREMENT_BCOUNT; 
   input INCREMENT_BCOUNT; 
   input ENABLE_IN; 
   output WRITE_ENABLE; 
   reg WRITE_ENABLE;
   output READ_ENABLE; 
   reg READ_ENABLE;

   reg INCREMENT_BCOUNT_CAPTURED; 
   reg INCREMENT_BCOUNT_METASTABLE; 
   reg INCREMENT; 
   reg[1:0] BUFFER_COUNT; 
   reg EMPTY; 
   reg FULL; 
   reg FULL_METASTABLE; 
   reg FULL_SYNCED; 

   always @(INCREMENT_BCOUNT or RESET or INCREMENT)
   begin
      if (RESET == 1'b1 | INCREMENT == 1'b1)
      begin
         INCREMENT_BCOUNT_CAPTURED <= 1'b0 ; 
      end
      else if (INCREMENT_BCOUNT == 1'b1)
      begin
         INCREMENT_BCOUNT_CAPTURED <= 1'b1 ; 
      end 
   end 

   always @(RD_CLK or RESET)
   begin
      if (RESET == 1'b1)
      begin
         INCREMENT_BCOUNT_METASTABLE <= 1'b0 ; 
         INCREMENT <= 1'b0 ; 
      end
      else if (RD_CLK == 1'b1)
      begin
         INCREMENT_BCOUNT_METASTABLE <= (INCREMENT_BCOUNT_CAPTURED & (~INCREMENT)) ; 
         INCREMENT <= (INCREMENT_BCOUNT_METASTABLE & (~INCREMENT)) ; 
      end 
   end 

   always @(RD_CLK or RESET)
   begin
      if (RESET == 1'b1)
      begin
         BUFFER_COUNT <= 0 ; 
         EMPTY <= 1'b1 ; 
         FULL <= 1'b0 ; 
      end
      else if (RD_CLK == 1'b1)
      begin
         if (DECREMENT_BCOUNT == 1'b1 & INCREMENT == 1'b0)
         begin
            BUFFER_COUNT <= BUFFER_COUNT - 1 ; 
         end
         else if (DECREMENT_BCOUNT == 1'b0 & INCREMENT == 1'b1)
         begin
            BUFFER_COUNT <= BUFFER_COUNT + 1 ; 
         end 
         if (BUFFER_COUNT == 0)
         begin
            EMPTY <= 1'b1 ; 
            FULL <= 1'b0 ; 
         end
         else if (BUFFER_COUNT == 2)
         begin
            EMPTY <= 1'b0 ; 
            FULL <= 1'b1 ; 
         end
         else
         begin
            EMPTY <= 1'b0 ; 
            FULL <= 1'b0 ; 
         end 
      end 
   end 

   always @(RD_CLK or RESET)
   begin
      if (RESET == 1'b1)
      begin
         READ_ENABLE <= 1'b0 ; 
      end
      else if (RD_CLK == 1'b1)
      begin
         if (ENABLE_READ_STALL == 1 & EMPTY == 1'b1)
         begin
            READ_ENABLE <= 1'b0 ; 
         end
         else
         begin
            READ_ENABLE <= 1'b1 ; 
         end 
      end 
   end 

   always @(WR_CLK or RESET)
   begin
      if (RESET == 1'b1)
      begin
         FULL_METASTABLE <= 1'b0 ; 
         FULL_SYNCED <= 1'b0 ; 
      end
      else if (WR_CLK == 1'b1)
      begin
         FULL_METASTABLE <= FULL ; 
         FULL_SYNCED <= FULL_METASTABLE ; 
      end 
   end 

   always @(WR_CLK or RESET)
   begin
      if (RESET == 1'b1)
      begin
         WRITE_ENABLE <= 1'b0 ; 
      end
      else if (WR_CLK == 1'b1)
      begin
         if (ENABLE_IN == 1'b0 | (ENABLE_WRITE_STALL == 1 & FULL_SYNCED == 1'b1))
         begin
            WRITE_ENABLE <= 1'b0 ; 
         end
         else
         begin
            WRITE_ENABLE <= 1'b1 ; 
         end 
      end 
   end 
endmodule