s2p8x32_s.v

包含了四位计数器等基本数字模块的的verilog HDL程序代码,该功能实现,可以直接利用DC进行综合,得到硬件电路,亦能够转换成VHDL语言进行综合

//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.34  Oct. 7, 2003 
// Wed Mar 10 16:54:37 2004
//
//      Input file         : /home/mcgett/temp/paulg/vhdl/s2p8x32.vhd
//      Design name        : S2P8X32
//      Author             : 
//      Company            : 
//
//      Description        : 
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
//
// The S2P8X32 module (Serial to Parallel convertor, 8 channels by 32 bit).  This module
// takes eight serial input streams and outputs eight 32 bit words. It consists of a delay
// module, eight 8X1 muxes, and thirty-two 16X1 dual-port RAMS.
//
module S2P8X32 (SERIAL_DATA, WRITE_ENABLE, WR_CLK, WRITE_ADDRESS, MSB_WR, DP_WR_EN, RESET, OE, RD_CLK, READ_ENABLE, FORCE_RD_ADDRESS_INC, ADJUST_ADDRESS_MASK, DATA_BANK_OUT);

`include "parameter_file.v"

   input[7:0] SERIAL_DATA; 
   input WRITE_ENABLE; 
   input WR_CLK; 
   input [23:0]WRITE_ADDRESS; 
   input[3:0] MSB_WR; 
   input[31:0] DP_WR_EN; 
   input RESET; 
   input OE; 
   input RD_CLK; 
   input READ_ENABLE; 
   input FORCE_RD_ADDRESS_INC; 
   input ADJUST_ADDRESS_MASK; 
   output[31:0] DATA_BANK_OUT; 
   reg[31:0] DATA_BANK_OUT;

   wire[7:0] DELAYED_DATA; 
   wire[7:0] MUXED_DATA; 
   wire[31:0] READ_DATA; 
   wire[31:0] REG_READ_DATA_A; 
   wire[31:0] REG_READ_DATA_B; 
   reg[3:0] READ_ADDRESS;
	
	wire[2:0] WRITE_ADDRESS_ARRAY [7:0]; 

	assign WRITE_ADDRESS_ARRAY[0][2:0] = WRITE_ADDRESS[2:0];
	assign WRITE_ADDRESS_ARRAY[1][2:0] = WRITE_ADDRESS[5:3];
	assign WRITE_ADDRESS_ARRAY[2][2:0] = WRITE_ADDRESS[8:6];
	assign WRITE_ADDRESS_ARRAY[3][2:0] = WRITE_ADDRESS[11:9];
	assign WRITE_ADDRESS_ARRAY[4][2:0] = WRITE_ADDRESS[14:12];
	assign WRITE_ADDRESS_ARRAY[5][2:0] = WRITE_ADDRESS[17:15];
	assign WRITE_ADDRESS_ARRAY[6][2:0] = WRITE_ADDRESS[20:18];
	assign WRITE_ADDRESS_ARRAY[7][2:0] = WRITE_ADDRESS[23:21];

//   genvar I;
//   generate
//       for (I=0; I < 8; I=I+1) 
//       begin: DELAY
//          U[I] #(I) (.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[I]), .DOUT(DELAYED_DATA[I]));
//       end
//   endgenerate


   DELAY U1_0(.DELAY_LENGTH(4'd0),.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[0]), .DOUT(DELAYED_DATA[0])); 
   DELAY U1_1(.DELAY_LENGTH(4'd1),.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[1]), .DOUT(DELAYED_DATA[1])); 
   DELAY U1_2(.DELAY_LENGTH(4'd2),.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[2]), .DOUT(DELAYED_DATA[2])); 
   DELAY U1_3(.DELAY_LENGTH(4'd3),.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[3]), .DOUT(DELAYED_DATA[3])); 
   DELAY U1_4(.DELAY_LENGTH(4'd4),.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[4]), .DOUT(DELAYED_DATA[4])); 
   DELAY U1_5(.DELAY_LENGTH(4'd5),.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[5]), .DOUT(DELAYED_DATA[5])); 
   DELAY U1_6(.DELAY_LENGTH(4'd6),.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[6]), .DOUT(DELAYED_DATA[6])); 
   DELAY U1_7(.DELAY_LENGTH(4'd7),.CLK(WR_CLK), .CE(WRITE_ENABLE), .DIN(SERIAL_DATA[7]), .DOUT(DELAYED_DATA[7]));
	 
   MUX_8X1 MUX1_0 (.DIN(DELAYED_DATA), .SEL(WRITE_ADDRESS_ARRAY[0]), .MUXOUT(MUXED_DATA[0]));
   MUX_8X1 MUX1_1 (.DIN(DELAYED_DATA), .SEL(WRITE_ADDRESS_ARRAY[1]), .MUXOUT(MUXED_DATA[1]));
   MUX_8X1 MUX1_2 (.DIN(DELAYED_DATA), .SEL(WRITE_ADDRESS_ARRAY[2]), .MUXOUT(MUXED_DATA[2]));
   MUX_8X1 MUX1_3 (.DIN(DELAYED_DATA), .SEL(WRITE_ADDRESS_ARRAY[3]), .MUXOUT(MUXED_DATA[3]));
   MUX_8X1 MUX1_4 (.DIN(DELAYED_DATA), .SEL(WRITE_ADDRESS_ARRAY[4]), .MUXOUT(MUXED_DATA[4]));
   MUX_8X1 MUX1_5 (.DIN(DELAYED_DATA), .SEL(WRITE_ADDRESS_ARRAY[5]), .MUXOUT(MUXED_DATA[5]));
   MUX_8X1 MUX1_6 (.DIN(DELAYED_DATA), .SEL(WRITE_ADDRESS_ARRAY[6]), .MUXOUT(MUXED_DATA[6]));
   MUX_8X1 MUX1_7 (.DIN(DELAYED_DATA), .SEL(WRITE_ADDRESS_ARRAY[7]), .MUXOUT(MUXED_DATA[7])); 


   RAM16X1D RAM0_0 (.WE(DP_WR_EN[0]), .D(MUXED_DATA[0]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[0][0]), .A1(WRITE_ADDRESS_ARRAY[0][1]), .A2(WRITE_ADDRESS_ARRAY[0][2]), .A3(MSB_WR[0]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[0]));
   RAM16X1D RAM0_1 (.WE(DP_WR_EN[1]), .D(MUXED_DATA[1]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[1][0]), .A1(WRITE_ADDRESS_ARRAY[1][1]), .A2(WRITE_ADDRESS_ARRAY[1][2]), .A3(MSB_WR[0]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[1]));
   RAM16X1D RAM0_2 (.WE(DP_WR_EN[2]), .D(MUXED_DATA[2]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[2][0]), .A1(WRITE_ADDRESS_ARRAY[2][1]), .A2(WRITE_ADDRESS_ARRAY[2][2]), .A3(MSB_WR[0]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[2]));
   RAM16X1D RAM0_3 (.WE(DP_WR_EN[3]), .D(MUXED_DATA[3]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[3][0]), .A1(WRITE_ADDRESS_ARRAY[3][1]), .A2(WRITE_ADDRESS_ARRAY[3][2]), .A3(MSB_WR[0]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[3]));
   RAM16X1D RAM0_4 (.WE(DP_WR_EN[4]), .D(MUXED_DATA[4]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[4][0]), .A1(WRITE_ADDRESS_ARRAY[4][1]), .A2(WRITE_ADDRESS_ARRAY[4][2]), .A3(MSB_WR[0]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[4]));
   RAM16X1D RAM0_5 (.WE(DP_WR_EN[5]), .D(MUXED_DATA[5]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[5][0]), .A1(WRITE_ADDRESS_ARRAY[5][1]), .A2(WRITE_ADDRESS_ARRAY[5][2]), .A3(MSB_WR[0]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[5]));
   RAM16X1D RAM0_6 (.WE(DP_WR_EN[6]), .D(MUXED_DATA[6]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[6][0]), .A1(WRITE_ADDRESS_ARRAY[6][1]), .A2(WRITE_ADDRESS_ARRAY[6][2]), .A3(MSB_WR[0]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[6]));
   RAM16X1D RAM0_7 (.WE(DP_WR_EN[7]), .D(MUXED_DATA[7]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[7][0]), .A1(WRITE_ADDRESS_ARRAY[7][1]), .A2(WRITE_ADDRESS_ARRAY[7][2]), .A3(MSB_WR[0]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[7]));
   RAM16X1D RAM1_8 (.WE(DP_WR_EN[8]), .D(MUXED_DATA[8 - 8]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[0][0]), .A1(WRITE_ADDRESS_ARRAY[0][1]), .A2(WRITE_ADDRESS_ARRAY[0][2]), .A3(MSB_WR[1]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[8]));
   RAM16X1D RAM1_9 (.WE(DP_WR_EN[9]), .D(MUXED_DATA[9 - 8]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[1][0]), .A1(WRITE_ADDRESS_ARRAY[1][1]), .A2(WRITE_ADDRESS_ARRAY[1][2]), .A3(MSB_WR[1]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[9]));
   RAM16X1D RAM1_10 (.WE(DP_WR_EN[10]), .D(MUXED_DATA[10 - 8]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[2][0]), .A1(WRITE_ADDRESS_ARRAY[2][1]), .A2(WRITE_ADDRESS_ARRAY[2][2]), .A3(MSB_WR[1]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[10]));
   RAM16X1D RAM1_11 (.WE(DP_WR_EN[11]), .D(MUXED_DATA[11 - 8]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[3][0]), .A1(WRITE_ADDRESS_ARRAY[3][1]), .A2(WRITE_ADDRESS_ARRAY[3][2]), .A3(MSB_WR[1]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[11]));
   RAM16X1D RAM1_12 (.WE(DP_WR_EN[12]), .D(MUXED_DATA[12 - 8]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[4][0]), .A1(WRITE_ADDRESS_ARRAY[4][1]), .A2(WRITE_ADDRESS_ARRAY[4][2]), .A3(MSB_WR[1]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[12]));
   RAM16X1D RAM1_13 (.WE(DP_WR_EN[13]), .D(MUXED_DATA[13 - 8]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[5][0]), .A1(WRITE_ADDRESS_ARRAY[5][1]), .A2(WRITE_ADDRESS_ARRAY[5][2]), .A3(MSB_WR[1]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[13]));
   RAM16X1D RAM1_14 (.WE(DP_WR_EN[14]), .D(MUXED_DATA[14 - 8]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[6][0]), .A1(WRITE_ADDRESS_ARRAY[6][1]), .A2(WRITE_ADDRESS_ARRAY[6][2]), .A3(MSB_WR[1]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[14]));
   RAM16X1D RAM1_15 (.WE(DP_WR_EN[15]), .D(MUXED_DATA[15 - 8]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[7][0]), .A1(WRITE_ADDRESS_ARRAY[7][1]), .A2(WRITE_ADDRESS_ARRAY[7][2]), .A3(MSB_WR[1]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[15]));
   RAM16X1D RAM2_16 (.WE(DP_WR_EN[16]), .D(MUXED_DATA[16 - 16]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[0][0]), .A1(WRITE_ADDRESS_ARRAY[0][1]), .A2(WRITE_ADDRESS_ARRAY[0][2]), .A3(MSB_WR[2]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[16]));
   RAM16X1D RAM2_17 (.WE(DP_WR_EN[17]), .D(MUXED_DATA[17 - 16]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[1][0]), .A1(WRITE_ADDRESS_ARRAY[1][1]), .A2(WRITE_ADDRESS_ARRAY[1][2]), .A3(MSB_WR[2]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[17]));
   RAM16X1D RAM2_18 (.WE(DP_WR_EN[18]), .D(MUXED_DATA[18 - 16]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[2][0]), .A1(WRITE_ADDRESS_ARRAY[2][1]), .A2(WRITE_ADDRESS_ARRAY[2][2]), .A3(MSB_WR[2]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[18]));
   RAM16X1D RAM2_19 (.WE(DP_WR_EN[19]), .D(MUXED_DATA[19 - 16]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[3][0]), .A1(WRITE_ADDRESS_ARRAY[3][1]), .A2(WRITE_ADDRESS_ARRAY[3][2]), .A3(MSB_WR[2]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[19]));
   RAM16X1D RAM2_20 (.WE(DP_WR_EN[20]), .D(MUXED_DATA[20 - 16]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[4][0]), .A1(WRITE_ADDRESS_ARRAY[4][1]), .A2(WRITE_ADDRESS_ARRAY[4][2]), .A3(MSB_WR[2]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[20]));
   RAM16X1D RAM2_21 (.WE(DP_WR_EN[21]), .D(MUXED_DATA[21 - 16]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[5][0]), .A1(WRITE_ADDRESS_ARRAY[5][1]), .A2(WRITE_ADDRESS_ARRAY[5][2]), .A3(MSB_WR[2]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[21]));
   RAM16X1D RAM2_22 (.WE(DP_WR_EN[22]), .D(MUXED_DATA[22 - 16]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[6][0]), .A1(WRITE_ADDRESS_ARRAY[6][1]), .A2(WRITE_ADDRESS_ARRAY[6][2]), .A3(MSB_WR[2]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[22]));
   RAM16X1D RAM2_23 (.WE(DP_WR_EN[23]), .D(MUXED_DATA[23 - 16]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[7][0]), .A1(WRITE_ADDRESS_ARRAY[7][1]), .A2(WRITE_ADDRESS_ARRAY[7][2]), .A3(MSB_WR[2]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[23]));
   RAM16X1D RAM3_24 (.WE(DP_WR_EN[24]), .D(MUXED_DATA[24 - 24]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[0][0]), .A1(WRITE_ADDRESS_ARRAY[0][1]), .A2(WRITE_ADDRESS_ARRAY[0][2]), .A3(MSB_WR[3]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[24]));
   RAM16X1D RAM3_25 (.WE(DP_WR_EN[25]), .D(MUXED_DATA[25 - 24]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[1][0]), .A1(WRITE_ADDRESS_ARRAY[1][1]), .A2(WRITE_ADDRESS_ARRAY[1][2]), .A3(MSB_WR[3]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[25]));
   RAM16X1D RAM3_26 (.WE(DP_WR_EN[26]), .D(MUXED_DATA[26 - 24]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[2][0]), .A1(WRITE_ADDRESS_ARRAY[2][1]), .A2(WRITE_ADDRESS_ARRAY[2][2]), .A3(MSB_WR[3]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[26]));
   RAM16X1D RAM3_27 (.WE(DP_WR_EN[27]), .D(MUXED_DATA[27 - 24]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[3][0]), .A1(WRITE_ADDRESS_ARRAY[3][1]), .A2(WRITE_ADDRESS_ARRAY[3][2]), .A3(MSB_WR[3]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[27]));
   RAM16X1D RAM3_28 (.WE(DP_WR_EN[28]), .D(MUXED_DATA[28 - 24]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[4][0]), .A1(WRITE_ADDRESS_ARRAY[4][1]), .A2(WRITE_ADDRESS_ARRAY[4][2]), .A3(MSB_WR[3]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[28]));
   RAM16X1D RAM3_29 (.WE(DP_WR_EN[29]), .D(MUXED_DATA[29 - 24]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[5][0]), .A1(WRITE_ADDRESS_ARRAY[5][1]), .A2(WRITE_ADDRESS_ARRAY[5][2]), .A3(MSB_WR[3]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[29]));
   RAM16X1D RAM3_30 (.WE(DP_WR_EN[30]), .D(MUXED_DATA[30 - 24]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[6][0]), .A1(WRITE_ADDRESS_ARRAY[6][1]), .A2(WRITE_ADDRESS_ARRAY[6][2]), .A3(MSB_WR[3]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[30]));																																				 							 	  
   RAM16X1D RAM3_31 (.WE(DP_WR_EN[31]), .D(MUXED_DATA[31 - 24]), .WCLK(WR_CLK), .A0(WRITE_ADDRESS_ARRAY[7][0]), .A1(WRITE_ADDRESS_ARRAY[7][1]), .A2(WRITE_ADDRESS_ARRAY[7][2]), .A3(MSB_WR[3]), .DPRA0(READ_ADDRESS[0]), .DPRA1(READ_ADDRESS[1]), .DPRA2(READ_ADDRESS[2]), .DPRA3(READ_ADDRESS[3]), .SPO(), .DPO(READ_DATA[31])); 

   always @(RD_CLK or RESET)
   begin
      if (RESET == 1'b1)
      begin
         READ_ADDRESS[3:0] <= 4'b0000 ; 
      end
      else if (RD_CLK == 1'b1)
      begin
         if (READ_ENABLE == 1'b1)
         begin
            if (OE == 1'b1 | (FORCE_RD_ADDRESS_INC == 1'b1 & ADJUST_ADDRESS_MASK == 1'b1))
            begin
               READ_ADDRESS <= READ_ADDRESS + 1 ; 
            end 
         end 
      end 
   end 

   always @(RD_CLK)
   begin
      if (RD_CLK == 1'b1)
      begin
         if (READ_ENABLE == 1'b1)
         begin
            begin : xhdl_7
               integer I;
               for(I = 0; I <= 31; I = I + 1)
               begin
                  DATA_BANK_OUT[I] <= READ_DATA[I] & OE ; 
               end
            end 
         end 
      end 
   end 
endmodule