wr_cntrl_w.v

包含了四位计数器等基本数字模块的的verilog HDL程序代码,该功能实现,可以直接利用DC进行综合,得到硬件电路,亦能够转换成VHDL语言进行综合

//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.34  Oct. 7, 2003 
// Wed Mar 10 16:55:06 2004
//
//      Input file         : /home/mcgett/temp/paulg/vhdl/wr_cntrl.vhd
//      Design name        : WR_CNTRL
//      Author             : 
//      Company            : 
//
//      Description        : 
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
//
// Write Control Logic - Consists of eight 3-bit, that count synchronously, with the counter
// that drives WADDR_A initializes to 0 at reset, WADDR_B initializes to 7, C to 6, etc. It also
// contains a 32-bit one-hot state-machine, which is just a 32 bit shift register, that initializes
// to FE000001 on reset.
//
module WR_CNTRL (DP_WR_EN, WA_MSB, WRITE_ADDRESS, CLK, RESET, INCREMENT_BCOUNT, WRITE_ENABLE);

   output[31:0] DP_WR_EN; 
   wire[31:0] DP_WR_EN;
   output[3:0] WA_MSB; 
   wire[3:0] WA_MSB;
   output [23:0]WRITE_ADDRESS; 
   input CLK; 
   input RESET; 
   output INCREMENT_BCOUNT; 
   reg INCREMENT_BCOUNT;
   input WRITE_ENABLE; 

   reg[31:0] DP_WR_EN_INT; 
   reg[3:0] WA_MSB_INT; 
   reg[4:0] BIT_COUNT;
	
	reg [2:0]WRITE_ADDRESS_ARRAY[7:0]; 
	integer i;


   assign DP_WR_EN = DP_WR_EN_INT ;
   assign WA_MSB = WA_MSB_INT ;

	assign WRITE_ADDRESS[2:0] = WRITE_ADDRESS_ARRAY[0][2:0];
	assign WRITE_ADDRESS[5:3] = WRITE_ADDRESS_ARRAY[1][2:0];
	assign WRITE_ADDRESS[8:6] = WRITE_ADDRESS_ARRAY[2][2:0];
	assign WRITE_ADDRESS[11:9] = WRITE_ADDRESS_ARRAY[3][2:0];
	assign WRITE_ADDRESS[14:12] = WRITE_ADDRESS_ARRAY[4][2:0];
	assign WRITE_ADDRESS[17:15] = WRITE_ADDRESS_ARRAY[5][2:0];
	assign WRITE_ADDRESS[20:18] = WRITE_ADDRESS_ARRAY[6][2:0];
	assign WRITE_ADDRESS[23:21] = WRITE_ADDRESS_ARRAY[7][2:0];

   always @(CLK or RESET) begin
      if (RESET == 1'b1) begin
         BIT_COUNT <= 0 ; 
         INCREMENT_BCOUNT <= 1'b0 ; 
      end
      else if (CLK == 1'b1) begin
         if (WRITE_ENABLE == 1'b1) begin
            BIT_COUNT <= BIT_COUNT + 1 ; 
            if (BIT_COUNT == 30) begin
               INCREMENT_BCOUNT <= 1'b1 ; 
            end
            else begin
               INCREMENT_BCOUNT <= 1'b0 ; 
            end 
         end 
      end 
   end 

   always @(CLK or RESET)
   begin : xhdl_9
      reg[4:0] TEMP; 
      if (RESET == 1'b1) begin
			for (i=0; i <= 7; i=i+1) begin
				WRITE_ADDRESS_ARRAY[i][2:0] <= 7-i;
			end 
	 	end
      else if (CLK == 1'b1) begin
         if (WRITE_ENABLE == 1'b1) begin
				for (i=0; i <= 7; i=i+1) begin
					  WRITE_ADDRESS_ARRAY[i][2:0] <= WRITE_ADDRESS_ARRAY[i][2:0] + 1;
				end
         end 
      end 
   end 

   always @(CLK or RESET)begin
      if (RESET == 1'b1) begin
         DP_WR_EN_INT <= 32'b11111111000000000000000000000000 ; 
      end
      else if (CLK == 1'b1) begin
         if (WRITE_ENABLE == 1'b1) begin
            DP_WR_EN_INT <= {DP_WR_EN_INT[30:0], DP_WR_EN_INT[31]} ; 
         end 
      end 
   end 

   always @(CLK or RESET) begin
      if (RESET == 1'b1) begin
         WA_MSB_INT <= 4'b1000 ; 
      end
      else if (CLK == 1'b1) begin
         if (WRITE_ENABLE == 1'b1) begin
            if ((DP_WR_EN_INT[8]) == 1'b1 & (DP_WR_EN_INT[7]) == 1'b0) begin
               WA_MSB_INT[0] <= ~(WA_MSB_INT[0]) ; 
            end 
            if ((DP_WR_EN_INT[16]) == 1'b1 & (DP_WR_EN_INT[15]) == 1'b0) begin
               WA_MSB_INT[1] <= ~(WA_MSB_INT[1]) ; 
            end 
            if ((DP_WR_EN_INT[24]) == 1'b1 & (DP_WR_EN_INT[23]) == 1'b0) begin
               WA_MSB_INT[2] <= ~(WA_MSB_INT[2]) ; 
            end 
            if ((DP_WR_EN_INT[0]) == 1'b1 & (DP_WR_EN_INT[31]) == 1'b0) begin
               WA_MSB_INT[3] <= ~(WA_MSB_INT[3]) ; 
            end 
         end 
      end 
   end 
endmodule