ser_par_lib.v

包含了四位计数器等基本数字模块的的verilog HDL程序代码,该功能实现,可以直接利用DC进行综合,得到硬件电路,亦能够转换成VHDL语言进行综合

module ser_par_lib();

//  integer PORTS = 43; 
   parameter [BANKS - 1:0] MASK = CREATE_MASK(PORTS, BANKS); 


   function [0:0] CREATE_MASK;
      input NUMBER_OF_SERIAL_PORTS; 
      integer NUMBER_OF_SERIAL_PORTS;
      input NUMBER_OF_BANKS; 
      integer NUMBER_OF_BANKS;

      reg[NUMBER_OF_BANKS - 1:0] TEMP; 

      begin
         if ((NUMBER_OF_SERIAL_PORTS % 8) == 0)
         begin
            begin : xhdl_0
               integer I;
               for(I = 0; I <= NUMBER_OF_BANKS - 1; I = I + 1)
               begin
                  TEMP[I] = 1'b0; 
               end
            end 
            CREATE_MASK = TEMP; 
         end
         else
         begin
            begin : xhdl_1
               integer I;
               for(I = 0; I <= (NUMBER_OF_SERIAL_PORTS - (7 * NUMBER_OF_BANKS) - 1); I = I + 1)
               begin
                  TEMP[I] = 1'b0; 
               end
            end 
            begin : xhdl_2
               integer I;
               for(I = (NUMBER_OF_SERIAL_PORTS - (7 * NUMBER_OF_BANKS)); I <= (NUMBER_OF_BANKS - 1); I = I + 1)
               begin
                  TEMP[I] = 1'b1; 
               end
            end 
            CREATE_MASK = TEMP; 
         end 
      end
   endfunction