parameter_file.v

包含了四位计数器等基本数字模块的的verilog HDL程序代码,该功能实现,可以直接利用DC进行综合,得到硬件电路,亦能够转换成VHDL语言进行综合

   parameter NUMBER_OF_SERIAL_PORTS  = 43; //modify as desired
   parameter NUMBER_OF_BANKS = 6;  //divide ports by 8 and round up 
   parameter NUMBER_OF_STAGES = 1; 	  // 0 for banks <5, 1 for banks <17, else 2 
   parameter ENABLE_READ_STALL = 1;   //set to 1 if read/write rates different, else 0
   parameter ENABLE_WRITE_STALL = 1;  //set to 1 if read/write rates different, else 0