output_pipeline_o.v

包含了四位计数器等基本数字模块的的verilog HDL程序代码,该功能实现,可以直接利用DC进行综合,得到硬件电路,亦能够转换成VHDL语言进行综合

//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.34  Oct. 7, 2003 
// Wed Mar 10 16:54:12 2004
//
//      Input file         : /home/mcgett/temp/paulg/vhdl/output_pipeline.vhd
//      Design name        : OUTPUT_PIPELINE
//      Author             : 
//      Company            : 
//
//      Description        : 
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
module OUTPUT_PIPELINE (DATA_IN, RD_CLK, READ_ENABLE, READ_ENABLE_OUT, DATA_OUT);

`include "parameter_file.v"

   input [2047:0]DATA_IN; 
   input RD_CLK; 
   input READ_ENABLE; 
   output READ_ENABLE_OUT; 
   wire READ_ENABLE_OUT;
   output[31:0] DATA_OUT; 
   wire[31:0] DATA_OUT;
   assign ZERO_32 = 32'b00000000000000000000000000000000; 
   reg [31:0]BANK_DATA[63:0]; 
   wire [31:0]TEMP_ARRAY_DATA[19:0];
	wire [3:0]TEMP_DELAY; 
 

	always @*
	begin:create_array_loop
	   integer i;
   	integer j;
		for (i=0; i < 64; i = i + 1) begin
			if (i <= NUMBER_OF_BANKS - 1) begin
				for (j=0; j < 32; j = j + 1) begin
					BANK_DATA[i][j] = DATA_IN[(i*32)+j];
				end
			end
			else begin
				BANK_DATA[i][31:0] = ZERO_32;
			end
		end
	end

	genvar i;
   generate
      if (NUMBER_OF_STAGES == 0) begin: STAGE0
         OR4X32_REG u0 (.BUSA(BANK_DATA[0][31:0]), .BUSB(BANK_DATA[1][31:0]), .BUSC(BANK_DATA[2][31:0]), .BUSD(BANK_DATA[3][31:0]), .CLK(RD_CLK), .DATA_OUT(DATA_OUT));
      end
      else if (NUMBER_OF_STAGES==1) begin: STAGE1
			for (i=0; i<4; i=i+1) begin: loopa
         	OR4X32_REG u0(.BUSA(BANK_DATA[(i*4)][31:0]), .BUSB(BANK_DATA[(i*4)+1][31:0]), .BUSC(BANK_DATA[(i*4)+2][31:0]), .BUSD(BANK_DATA[(i*4)+3][31:0]), .CLK(RD_CLK), .DATA_OUT(TEMP_ARRAY_DATA[i][31:0]));
			end
         OR4X32_REG u4(.BUSA(TEMP_ARRAY_DATA[0][31:0]), .BUSB(TEMP_ARRAY_DATA[1][31:0]), .BUSC(TEMP_ARRAY_DATA[2][31:0]), .BUSD(TEMP_ARRAY_DATA[3][31:0]), .CLK(RD_CLK), .DATA_OUT(DATA_OUT));
      end
      else begin: STAGE2
			for (i=0; i<16; i=i+1) begin: loopb
         	OR4X32_REG u0(.BUSA(BANK_DATA[(i*4)][31:0]), .BUSB(BANK_DATA[(i*4)+1][31:0]), .BUSC(BANK_DATA[(i*4)+2][31:0]), .BUSD(BANK_DATA[(i*4)+3][31:0]), .CLK(RD_CLK), .DATA_OUT(TEMP_ARRAY_DATA[i][31:0]));
			end
			for (i=0; i<16; i=i+1) begin: loopc
         	OR4X32_REG u16(.BUSA(TEMP_ARRAY_DATA[(i*4)][31:0]), .BUSB(TEMP_ARRAY_DATA[(i*4)+1][31:0]), .BUSC(TEMP_ARRAY_DATA[(i*4)+2][31:0]), .BUSD(TEMP_ARRAY_DATA[(i*4)+3][31:0]), .CLK(RD_CLK), .DATA_OUT(TEMP_ARRAY_DATA[i+16][31:0]));
			end
         OR4X32_REG u20(.BUSA(TEMP_ARRAY_DATA[16][31:0]), .BUSB(TEMP_ARRAY_DATA[17][31:0]), .BUSC(TEMP_ARRAY_DATA[18][31:0]), .BUSD(TEMP_ARRAY_DATA[19][31:0]), .CLK(RD_CLK), .DATA_OUT(DATA_OUT));
     end
	endgenerate
	assign TEMP_DELAY = NUMBER_OF_STAGES + 1;
   DELAY DELAY1(.DELAY_LENGTH(TEMP_DELAY), .CLK(RD_CLK), .CE(VCC), .DIN(READ_ENABLE), .DOUT(READ_ENABLE_OUT)); 
endmodule