rd_cntrl_r.v

包含了四位计数器等基本数字模块的的verilog HDL程序代码,该功能实现,可以直接利用DC进行综合,得到硬件电路,亦能够转换成VHDL语言进行综合

//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.34  Oct. 7, 2003 
// Wed Mar 10 16:54:20 2004
//
//      Input file         : /home/mcgett/temp/paulg/vhdl/rd_cntrl.vhd
//      Design name        : RD_CNTRL
//      Author             : 
//      Company            : 
//
//      Description        : 
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
//
// Sychronizer circuit, and read control, as well as stall generation. Assumes that read port
// cannot keep up with the write circuit, and hence generates a stall signal that disables the
// write port.  The source of the data must stop inputing data until the stall goes away.
// Signalling between the read and write circuits is double buffered to prevent metastability.
//
module RD_CNTRL (RESET, CLK, READ_ENABLE, DECREMENT_BCOUNT, READ_COUNT, FORCE_RD_ADDRESS_INC, OE);

`include "parameter_file.v"

   input RESET; 
   input CLK; 
   input READ_ENABLE; 
   output DECREMENT_BCOUNT; 
   reg DECREMENT_BCOUNT;
   output [7:0] READ_COUNT; 
//   integer READ_COUNT_OUT;
   output FORCE_RD_ADDRESS_INC; 
   reg FORCE_RD_ADDRESS_INC;
   output[NUMBER_OF_BANKS - 1:0] OE; 
   wire[NUMBER_OF_BANKS - 1:0] OE;

   reg[7:0] READ_COUNT; 
   reg[NUMBER_OF_BANKS - 1:0] OE_INT; 

   assign OE = OE_INT ;
//  assign READ_COUNT_OUT = READ_COUNT ;

   always @(CLK or RESET)
   begin : READ_CTR
      if (RESET == 1'b1) begin
         DECREMENT_BCOUNT <= 1'b0 ; 
         READ_COUNT <= 0 ; 
      end
      else if (CLK == 1'b1) begin
         if (READ_ENABLE == 1'b1)
         begin
            if (READ_COUNT == NUMBER_OF_SERIAL_PORTS - 4) begin
               READ_COUNT <= READ_COUNT + 1 ; 
               DECREMENT_BCOUNT <= 1'b1 ; 
            end
            else if (READ_COUNT == NUMBER_OF_SERIAL_PORTS - 3) begin
               READ_COUNT <= READ_COUNT + 1 ; 
               DECREMENT_BCOUNT <= 1'b0 ; 
            end
            else if (READ_COUNT == NUMBER_OF_SERIAL_PORTS - 1) begin
               READ_COUNT <= 0 ; 
               DECREMENT_BCOUNT <= 1'b0 ; 
            end
            else begin
               READ_COUNT <= READ_COUNT + 1 ; 
               DECREMENT_BCOUNT <= 1'b0 ; 
            end 
         end 
      end 
   end 

   always @(CLK or RESET)
   begin
      if (RESET == 1'b1) begin
         FORCE_RD_ADDRESS_INC <= 1'b0 ; 
         OE_INT[0] <= 1'b1 ; 
         begin : xhdl_5
            integer I;
            for(I = 1; I <= (NUMBER_OF_BANKS - 1); I = I + 1) begin
               OE_INT[I] <= 1'b0 ; 
            end
         end 
      end
      else if (CLK == 1'b1) begin
         if (READ_ENABLE == 1'b1) begin
            if (READ_COUNT != NUMBER_OF_SERIAL_PORTS - 1) begin
               FORCE_RD_ADDRESS_INC <= 1'b0 ; 
               OE_INT[NUMBER_OF_BANKS - 1:0] <= {OE_INT[NUMBER_OF_BANKS - 2:0], OE_INT[NUMBER_OF_BANKS - 1]} ; 
            end
            else begin
               FORCE_RD_ADDRESS_INC <= 1'b1 ; 
               OE_INT[0] <= 1'b1 ; 
               begin : xhdl_7
                  integer I;
                  for(I = 1; I <= (NUMBER_OF_BANKS - 1); I = I + 1) begin
                     OE_INT[I] <= 1'b0 ; 
                  end
               end 
            end 
         end 
      end 
   end 
endmodule