phase_shift_sin.map.qmsg

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· QMSG 代码 · 共 62 行 · 第 1/4 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 10 09:01:57 2007 " "Info: Processing started: Thu May 10 09:01:57 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off phase_shift_sin -c phase_shift_sin " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off phase_shift_sin -c phase_shift_sin" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sin_rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sin_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_rom-SYN " "Info: Found design unit 1: sin_rom-SYN" {  } { { "sin_rom.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/sin_rom.vhd" 55 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sin_rom " "Info: Found entity 1: sin_rom" {  } { { "sin_rom.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/sin_rom.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder8-SYN " "Info: Found design unit 1: adder8-SYN" {  } { { "adder8.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/adder8.vhd" 55 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adder8 " "Info: Found entity 1: adder8" {  } { { "adder8.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/adder8.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder32.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder32-SYN " "Info: Found design unit 1: adder32-SYN" {  } { { "adder32.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/adder32.vhd" 55 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adder32 " "Info: Found entity 1: adder32" {  } { { "adder32.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/adder32.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "phase_shift_sin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file phase_shift_sin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 phase_shift_sin-behave " "Info: Found design unit 1: phase_shift_sin-behave" {  } { { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 phase_shift_sin " "Info: Found entity 1: phase_shift_sin" {  } { { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "phase_shift_sin " "Info: Elaborating entity \"phase_shift_sin\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder32 adder32:u1 " "Info: Elaborating entity \"adder32\" for hierarchy \"adder32:u1\"" {  } { { "phase_shift_sin.vhd" "u1" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub adder32:u1\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"adder32:u1\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "adder32.vhd" "lpm_add_sub_component" { Text "E:/老项目/数字移相信号发生器/fpga/adder32.vhd" 78 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore adder32:u1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"adder32:u1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\"" {  } { { "lpm_add_sub.tdf" "adder" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer adder32:u1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:oflow_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"adder32:u1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:oflow_node\"" {  } { { "addcore.tdf" "oflow_node" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 94 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer adder32:u1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"adder32:u1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}