phase_shift_sin.map.qmsg

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· QMSG 代码 · 共 62 行 · 第 1/4 页

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5hb2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5hb2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5hb2 " "Info: Found entity 1: altsyncram_5hb2" {  } { { "db/altsyncram_5hb2.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/altsyncram_5hb2.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_sia.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_sia.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_sia " "Info: Found entity 1: cntr_sia" {  } { { "db/cntr_sia.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_sia.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_09b.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_09b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_09b " "Info: Found entity 1: cntr_09b" {  } { { "db/cntr_09b.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_09b.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|clk acq_clk " "Info: Source node \"\|phase_shift_sin\|clk\" connects to port \"acq_clk\"" {  } { { "phase_shift_sin.vhd" "clk" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 6 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fout\[0\] acq_data_in\[0\] " "Info: Source node \"\|phase_shift_sin\|fout\[0\]\" connects to port \"acq_data_in\[0\]\"" {  } { { "phase_shift_sin.vhd" "fout\[0\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fout\[1\] acq_data_in\[1\] " "Info: Source node \"\|phase_shift_sin\|fout\[1\]\" connects to port \"acq_data_in\[1\]\"" {  } { { "phase_shift_sin.vhd" "fout\[1\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fout\[2\] acq_data_in\[2\] " "Info: Source node \"\|phase_shift_sin\|fout\[2\]\" connects to port \"acq_data_in\[2\]\"" {  } { { "phase_shift_sin.vhd" "fout\[2\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fout\[3\] acq_data_in\[3\] " "Info: Source node \"\|phase_shift_sin\|fout\[3\]\" connects to port \"acq_data_in\[3\]\"" {  } { { "phase_shift_sin.vhd" "fout\[3\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fout\[4\] acq_data_in\[4\] " "Info: Source node \"\|phase_shift_sin\|fout\[4\]\" connects to port \"acq_data_in\[4\]\"" {  } { { "phase_shift_sin.vhd" "fout\[4\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fout\[5\] acq_data_in\[5\] " "Info: Source node \"\|phase_shift_sin\|fout\[5\]\" connects to port \"acq_data_in\[5\]\"" {  } { { "phase_shift_sin.vhd" "fout\[5\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fout\[6\] acq_data_in\[6\] " "Info: Source node \"\|phase_shift_sin\|fout\[6\]\" connects to port \"acq_data_in\[6\]\"" {  } { { "phase_shift_sin.vhd" "fout\[6\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fout\[7\] acq_data_in\[7\] " "Info: Source node \"\|phase_shift_sin\|fout\[7\]\" connects to port \"acq_data_in\[7\]\"" {  } { { "phase_shift_sin.vhd" "fout\[7\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fword\[0\] acq_data_in\[8\] " "Info: Source node \"\|phase_shift_sin\|fword\[0\]\" connects to port \"acq_data_in\[8\]\"" {  } { { "phase_shift_sin.vhd" "fword\[0\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fword\[1\] acq_data_in\[9\] " "Info: Source node \"\|phase_shift_sin\|fword\[1\]\" connects to port \"acq_data_in\[9\]\"" {  } { { "phase_shift_sin.vhd" "fword\[1\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fword\[2\] acq_data_in\[10\] " "Info: Source node \"\|phase_shift_sin\|fword\[2\]\" connects to port \"acq_data_in\[10\]\"" {  } { { "phase_shift_sin.vhd" "fword\[2\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fword\[3\] acq_data_in\[11\] " "Info: Source node \"\|phase_shift_sin\|fword\[3\]\" connects to port \"acq_data_in\[11\]\"" {  } { { "phase_shift_sin.vhd" "fword\[3\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fword\[4\] acq_data_in\[12\] " "Info: Source node \"\|phase_shift_sin\|fword\[4\]\" connects to port \"acq_data_in\[12\]\"" {  } { { "phase_shift_sin.vhd" "fword\[4\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fword\[5\] acq_data_in\[13\] " "Info: Source node \"\|phase_shift_sin\|fword\[5\]\" connects to port \"acq_data_in\[13\]\"" {  } { { "phase_shift_sin.vhd" "fword\[5\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fword\[6\] acq_data_in\[14\] " "Info: Source node \"\|phase_shift_sin\|fword\[6\]\" connects to port \"acq_data_in\[14\]\"" {  } { { "phase_shift_sin.vhd" "fword\[6\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|fword\[7\] acq_data_in\[15\] " "Info: Source node \"\|phase_shift_sin\|fword\[7\]\" connects to port \"acq_data_in\[15\]\"" {  } { { "phase_shift_sin.vhd" "fword\[7\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pout\[0\] acq_data_in\[16\] " "Info: Source node \"\|phase_shift_sin\|pout\[0\]\" connects to port \"acq_data_in\[16\]\"" {  } { { "phase_shift_sin.vhd" "pout\[0\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pout\[1\] acq_data_in\[17\] " "Info: Source node \"\|phase_shift_sin\|pout\[1\]\" connects to port \"acq_data_in\[17\]\"" {  } { { "phase_shift_sin.vhd" "pout\[1\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pout\[2\] acq_data_in\[18\] " "Info: Source node \"\|phase_shift_sin\|pout\[2\]\" connects to port \"acq_data_in\[18\]\"" {  } { { "phase_shift_sin.vhd" "pout\[2\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pout\[3\] acq_data_in\[19\] " "Info: Source node \"\|phase_shift_sin\|pout\[3\]\" connects to port \"acq_data_in\[19\]\"" {  } { { "phase_shift_sin.vhd" "pout\[3\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pout\[4\] acq_data_in\[20\] " "Info: Source node \"\|phase_shift_sin\|pout\[4\]\" connects to port \"acq_data_in\[20\]\"" {  } { { "phase_shift_sin.vhd" "pout\[4\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pout\[5\] acq_data_in\[21\] " "Info: Source node \"\|phase_shift_sin\|pout\[5\]\" connects to port \"acq_data_in\[21\]\"" {  } { { "phase_shift_sin.vhd" "pout\[5\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pout\[6\] acq_data_in\[22\] " "Info: Source node \"\|phase_shift_sin\|pout\[6\]\" connects to port \"acq_data_in\[22\]\"" {  } { { "phase_shift_sin.vhd" "pout\[6\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pout\[7\] acq_data_in\[23\] " "Info: Source node \"\|phase_shift_sin\|pout\[7\]\" connects to port \"acq_data_in\[23\]\"" {  } { { "phase_shift_sin.vhd" "pout\[7\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 7 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pword\[0\] acq_data_in\[24\] " "Info: Source node \"\|phase_shift_sin\|pword\[0\]\" connects to port \"acq_data_in\[24\]\"" {  } { { "phase_shift_sin.vhd" "pword\[0\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pword\[1\] acq_data_in\[25\] " "Info: Source node \"\|phase_shift_sin\|pword\[1\]\" connects to port \"acq_data_in\[25\]\"" {  } { { "phase_shift_sin.vhd" "pword\[1\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pword\[2\] acq_data_in\[26\] " "Info: Source node \"\|phase_shift_sin\|pword\[2\]\" connects to port \"acq_data_in\[26\]\"" {  } { { "phase_shift_sin.vhd" "pword\[2\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pword\[3\] acq_data_in\[27\] " "Info: Source node \"\|phase_shift_sin\|pword\[3\]\" connects to port \"acq_data_in\[27\]\"" {  } { { "phase_shift_sin.vhd" "pword\[3\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pword\[4\] acq_data_in\[28\] " "Info: Source node \"\|phase_shift_sin\|pword\[4\]\" connects to port \"acq_data_in\[28\]\"" {  } { { "phase_shift_sin.vhd" "pword\[4\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pword\[5\] acq_data_in\[29\] " "Info: Source node \"\|phase_shift_sin\|pword\[5\]\" connects to port \"acq_data_in\[29\]\"" {  } { { "phase_shift_sin.vhd" "pword\[5\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pword\[6\] acq_data_in\[30\] " "Info: Source node \"\|phase_shift_sin\|pword\[6\]\" connects to port \"acq_data_in\[30\]\"" {  } { { "phase_shift_sin.vhd" "pword\[6\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|phase_shift_sin\|pword\[7\] acq_data_in\[31\] " "Info: Source node \"\|phase_shift_sin\|pword\[7\]\" connects to port \"acq_data_in\[31\]\"" {  } { { "phase_shift_sin.vhd" "pword\[7\]" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0}  } {  } 0 0 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1018 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1003 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "db/decode_9ie.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/decode_9ie.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[0\] data_in GND " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[0\]\" with stuck data_in port to stuck value GND" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 516 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff data_in GND " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff\" with stuck data_in port to stuck value GND" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" 309 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "632 " "Info: Implemented 632 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "20 " "Info: Implemented 20 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "546 " "Info: Implemented 546 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "48 " "Info: Implemented 48 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 10 09:02:21 2007 " "Info: Processing ended: Thu May 10 09:02:21 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Info: Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}