adc.map.qmsg

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· QMSG 代码 · 共 189 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 29 11:21:06 2007 " "Info: Processing started: Sat Dec 29 11:21:06 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adc -c adc " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc -c adc" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../did.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../did.v" { { "Info" "ISGN_ENTITY_NAME" "1 did " "Info: Found entity 1: did" {  } { { "../did.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/did.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adc_4/adc_4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../adc_4/adc_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 adc_4 " "Info: Found entity 1: adc_4" {  } { { "../adc_4/adc_4.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc_4.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adc_3/adc_3.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../adc_3/adc_3.v" { { "Info" "ISGN_ENTITY_NAME" "1 adc_3 " "Info: Found entity 1: adc_3" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adc_2/adc_2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../adc_2/adc_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 adc_2 " "Info: Found entity 1: adc_2" {  } { { "../adc_2/adc_2.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/adc_2.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adc_1/adc_1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../adc_1/adc_1.v" { { "Info" "ISGN_ENTITY_NAME" "1 adc_1 " "Info: Found entity 1: adc_1" {  } { { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adc_4/adc.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../adc_4/adc.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adc " "Info: Found entity 1: adc" {  } { { "../adc_4/adc.bdf" "" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adc " "Info: Elaborating entity \"adc\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adc_1 adc_1:inst " "Info: Elaborating entity \"adc_1\" for hierarchy \"adc_1:inst\"" {  } { { "../adc_4/adc.bdf" "inst" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { -8 440 576 88 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "add_out\[2\] adc_1.v(5) " "Warning: Output port \"add_out\[2\]\" at adc_1.v(5) has no driver" {  } { { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 5 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "add_out\[1\] adc_1.v(5) " "Warning: Output port \"add_out\[1\]\" at adc_1.v(5) has no driver" {  } { { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 5 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "add_out\[0\] adc_1.v(5) " "Warning: Output port \"add_out\[0\]\" at adc_1.v(5) has no driver" {  } { { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 5 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "did did:inst3 " "Info: Elaborating entity \"did\" for hierarchy \"did:inst3\"" {  } { { "../adc_4/adc.bdf" "inst3" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { -168 200 328 -72 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adc_4 adc_4:inst11 " "Info: Elaborating entity \"adc_4\" for hierarchy \"adc_4:inst11\"" {  } { { "../adc_4/adc.bdf" "inst11" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { 8 168 264 104 "inst11" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adc_3 adc_3:inst10 " "Info: Elaborating entity \"adc_3\" for hierarchy \"adc_3:inst10\"" {  } { { "../adc_4/adc.bdf" "inst10" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { -264 872 1064 -168 "inst10" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adc_2 adc_2:inst1 " "Info: Elaborating entity \"adc_2\" for hierarchy \"adc_2:inst1\"" {  } { { "../adc_4/adc.bdf" "inst1" { Schematic "D:/altera/qdesigns50/zdx/ADC模块_r/adc_4/adc.bdf" { { -264 480 600 -72 "inst1" "" } } } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "adc_1:inst\|beg High " "Info: Power-up level of register \"adc_1:inst\|beg\" is not specified -- using power-up level of High to minimize register" {  } { { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 6 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_1:inst\|beg data_in VCC " "Warning: Reduced register \"adc_1:inst\|beg\" with stuck data_in port to stuck value VCC" {  } { { "../adc_1/adc_1.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_1/adc_1.v" 6 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[11\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[11\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[11\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[11\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[10\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[10\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[10\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[10\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[9\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[9\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[9\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[9\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[8\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[8\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[8\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[8\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[7\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[7\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[7\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[7\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[6\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[6\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[6\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[6\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[5\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[5\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[5\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[5\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[4\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[4\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[4\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[4\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst14\|data_out\[3\] " "Warning: No clock transition on register \"adc_3:inst14\|data_out\[3\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst14\|data_out\[3\] clock_enable GND " "Warning: Reduced register \"adc_3:inst14\|data_out\[3\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}