adc.map.qmsg

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· QMSG 代码 · 共 189 行 · 第 1/5 页

{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst5\|data_out\[7\] " "Warning: No clock transition on register \"adc_3:inst5\|data_out\[7\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst5\|data_out\[7\] clock_enable GND " "Warning: Reduced register \"adc_3:inst5\|data_out\[7\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst5\|data_out\[6\] " "Warning: No clock transition on register \"adc_3:inst5\|data_out\[6\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst5\|data_out\[6\] clock_enable GND " "Warning: Reduced register \"adc_3:inst5\|data_out\[6\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst5\|data_out\[5\] " "Warning: No clock transition on register \"adc_3:inst5\|data_out\[5\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst5\|data_out\[5\] clock_enable GND " "Warning: Reduced register \"adc_3:inst5\|data_out\[5\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst5\|data_out\[4\] " "Warning: No clock transition on register \"adc_3:inst5\|data_out\[4\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst5\|data_out\[4\] clock_enable GND " "Warning: Reduced register \"adc_3:inst5\|data_out\[4\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst5\|data_out\[3\] " "Warning: No clock transition on register \"adc_3:inst5\|data_out\[3\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst5\|data_out\[3\] clock_enable GND " "Warning: Reduced register \"adc_3:inst5\|data_out\[3\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst5\|data_out\[2\] " "Warning: No clock transition on register \"adc_3:inst5\|data_out\[2\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst5\|data_out\[2\] clock_enable GND " "Warning: Reduced register \"adc_3:inst5\|data_out\[2\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst5\|data_out\[1\] " "Warning: No clock transition on register \"adc_3:inst5\|data_out\[1\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst5\|data_out\[1\] clock_enable GND " "Warning: Reduced register \"adc_3:inst5\|data_out\[1\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst5\|data_out\[0\] " "Warning: No clock transition on register \"adc_3:inst5\|data_out\[0\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst5\|data_out\[0\] clock_enable GND " "Warning: Reduced register \"adc_3:inst5\|data_out\[0\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[11\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[11\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[11\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[11\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[10\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[10\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[10\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[10\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[9\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[9\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[9\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[9\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[8\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[8\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[8\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[8\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[7\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[7\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[7\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[7\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[6\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[6\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[6\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[6\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[5\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[5\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[5\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[5\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[4\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[4\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[4\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[4\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[3\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[3\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[3\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[3\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[2\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[2\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[2\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[2\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "adc_3:inst4\|data_out\[1\] " "Warning: No clock transition on register \"adc_3:inst4\|data_out\[1\]\" due to stuck clock or clock enable" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adc_3:inst4\|data_out\[1\] clock_enable GND " "Warning: Reduced register \"adc_3:inst4\|data_out\[1\]\" with stuck clock_enable port to stuck value GND" {  } { { "../adc_3/adc_3.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_3/adc_3.v" 5 -1 0 } }  } 0}