dac.tan.rpt

VHDL語言實驗數字鍾功能,可手動調時,設定閙鍾等

; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30TC144-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLK1            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                           ; To                                                             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------------------------------------------------------+----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[11] ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[10] ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[9]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[8]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[7]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[6]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[5]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[2]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[1]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 108.70 MHz ( period = 9.200 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[0]  ; CLK        ; CLK      ; None                        ; None                      ; 8.100 ns                ;
; N/A   ; 109.89 MHz ( period = 9.100 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[2]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[11] ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 109.89 MHz ( period = 9.100 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[1]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[11] ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 109.89 MHz ( period = 9.100 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[2]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[10] ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 109.89 MHz ( period = 9.100 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[1]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[10] ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 109.89 MHz ( period = 9.100 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[2]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[9]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 109.89 MHz ( period = 9.100 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[1]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[9]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 109.89 MHz ( period = 9.100 ns )               ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[2]  ; lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[8]  ; CLK        ; CLK      ; None                        ; None                      ; 8.000 ns                ;