addr_8.vhd

里面含大量VHDL设计原代码

library IEEE;
use IEEE.std_logic_1164.all;

entity addr is
    port (
        a: in STD_LOGIC;
        b: in STD_LOGIC;
        ci: in STD_LOGIC;
        sum: out STD_LOGIC;
        co: out STD_LOGIC
    );
end addr;

architecture addr_arch of addr is
begin
 sum<= a xor b xor ci ;
 co <= (( a or b) and ci) or ( a and b);
  -- <<enter your statements here>>
end addr_arch;

library IEEE;
use IEEE.std_logic_1164.all;

entity addr_8 is
    port (
        CI: in STD_LOGIC;
        a: in STD_LOGIC_VECTOR (7 downto 0);
        b: in STD_LOGIC_VECTOR (7 downto 0);
        sum: out STD_LOGIC_VECTOR (7 downto 0);
        CO: out STD_LOGIC
    );
end addr_8;

architecture addr_8_arch of addr_8 is
component adder
	port ( ci: IN std_logic;
	 	a,b: IN std_logic;
	 	sum ,co: OUT std_logic );
	 end component ;

signal c:std_logic_vector ( 7 downto 1 );
	 		
begin
u1: adder port map ( ci ,a( 0 ),b( 0 ), sum( 0 ) ,c( 1 ));
u2: adder port map ( c(1) ,a( 1 ),b( 1 ), sum( 1 ) ,c( 2 ));
u3: adder port map ( c(2) ,a( 2 ),b( 2 ), sum( 2 ) ,c( 3 ));
u4: adder port map ( c(3) ,a( 3 ),b( 3 ), sum( 3 ) ,c( 4 ));
u5: adder port map ( c(4) ,a( 4 ),b( 4 ), sum( 4 ) ,c( 5 ));
u6: adder port map ( c(5) ,a( 5 ),b( 5 ), sum( 5 ) ,c( 6 ));
u7: adder port map ( c(6) ,a( 6 ),b( 6 ), sum( 6 ) ,c( 7 ));
u8: adder port map ( c(7) ,a( 7 ),b( 7 ), sum( 7 ) ,co );

  -- <<enter your statements here>>
end addr_8_arch;