来自「里面含大量VHDL设计原代码」· 代码 · 共 30 行

library IEEE;
use IEEE.std_logic_1164.all;

entity eqcomp4 is
    port (
        a: in STD_LOGIC_VECTOR (3 downto 0);
        b: in STD_LOGIC_VECTOR (3 downto 0);
        equals: out STD_LOGIC
    );
end eqcomp4;

architecture eqcomp4_arch of eqcomp4 is
signal x: std_logic_vector(0 to 3);
component xnor2
    port(a,b:in std_logic;
           z:out std_logic);
     end component;
     component and4
     port(a,b,c,d:in std_logic;
                y:out std_logic);
     end component;      
begin
  U0: xnor2 port map(a(0),b(0),x(0));
  U1: xnor2 port map(a(1),b(1),x(1));
  U2: xnor2 port map(a(2),b(2),x(2));
  U3: xnor2 port map(a(3),b(3),x(3));
  U4: and4  port map(x(0),x(1),x(2),x(3),equals);
  -- <<enter your statements here>>
end eqcomp4_arch;