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里面含大量VHDL设计原代码

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan is
    port (
        b: in STD_LOGIC_VECTOR (3 downto 0);
        row: buffer STD_LOGIC_VECTOR (3 downto 0);
        c: out STD_LOGIC_VECTOR (3 downto 0);
        clk: in STD_LOGIC;
        r: in STD_LOGIC
    );
end scan;

architecture scan_arch of scan is

signal dd:STD_LOGIC_VECTOR (1 downto 0);
signal dd1:STD_LOGIC_VECTOR (1 downto 0);
signal line:STD_LOGIC_VECTOR (1 downto 0);
signal keydown:std_logic;

begin

count: process (r, clk  )
	begin
	if ( r='1' ) then dd<="00";
	elsif( clk'event and clk = '1') then
			dd <= dd + '1';
			end if ;
end process count ;
 with dd select
   row<="0111"when"00",
     	"1011"when"01",
     	"1101"when"10",
     	"1110"when"11",
     	"ZZZZ"when others ;

with row select
   	  dd1<= "00"when"0111",
     		"01"when"1011",
     		"10"when"1101",
     		"11"when"1110",
     		"ZZ"when others ;
   
keydown<= b(0) and b(1) and b(2) and b(3) ;

with b select
  line<="00"when"0111",
  	"01"when"1011",
     	"10"when"1101",
     	"11"when"1110",
     	"ZZ"when others ;

process ( keydown,clk,r  )
begin
if ( r='1' ) then c<="0000";
	elsif( clk'event and clk = '1') then
   			if (keydown = '0') then
      c <= dd1&line ;
    end if;
    end if;
end process ;

end scan_arch;