i2c.twr

清华大学verilog hdl源码例子

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml i2c i2c.ncd -o i2c.twr
i2c.pcf


Design file:              i2c.ncd
Physical constraint file: i2c.pcf
Device,speed:             xc2s200,-5 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clock
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
sda_pin     |    2.436(R)|   -0.737(R)|clock_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clock to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
i2c_rdata<0>|   10.369(R)|clock_BUFGP       |   0.000|
i2c_rdata<1>|    7.665(R)|clock_BUFGP       |   0.000|
i2c_rdata<2>|    7.665(R)|clock_BUFGP       |   0.000|
i2c_rdata<3>|    7.665(R)|clock_BUFGP       |   0.000|
i2c_rdata<4>|    7.665(R)|clock_BUFGP       |   0.000|
i2c_rdata<5>|    7.665(R)|clock_BUFGP       |   0.000|
i2c_rdata<6>|    7.665(R)|clock_BUFGP       |   0.000|
i2c_rdata<7>|    7.665(R)|clock_BUFGP       |   0.000|
scl_pin     |   12.533(R)|clock_BUFGP       |   0.000|
sda_pin     |    8.215(R)|clock_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |   13.215|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sun Feb 26 18:30:46 2006
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Peak Memory Usage: 47 MB