i2c.par

清华大学verilog hdl源码例子

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

TOMWANG::  Sun Feb 26 18:30:39 2006


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 i2c_map.ncd i2c.ncd
i2c.pcf 


Constraints file: i2c.pcf

Loading device database for application Par from file "i2c_map.ncd".
   "i2c" is an NCD, version 2.38, device xc2s200, package pq208, speed -5
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <sda_pin> must be placed at site P35.
Resolved that IOB <i2c_rdata<0>> must be placed at site P14.
Resolved that IOB <i2c_rdata<1>> must be placed at site P18.
Resolved that IOB <i2c_rdata<2>> must be placed at site P16.
Resolved that IOB <i2c_rdata<3>> must be placed at site P21.
Resolved that IOB <i2c_rdata<4>> must be placed at site P23.
Resolved that IOB <i2c_rdata<5>> must be placed at site P27.
Resolved that IOB <i2c_rdata<6>> must be placed at site P30.
Resolved that IOB <i2c_rdata<7>> must be placed at site P33.
Resolved that IOB <scl_pin> must be placed at site P37.
Resolved that GCLKIOB <clock> must be placed at site P80.
Resolved that IOB <rst_l> must be placed at site P163.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            11 out of 140     7%
      Number of LOCed External IOBs   11 out of 11    100%

   Number of SLICEs                   83 out of 2352    3%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989850) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.......
Phase 5.8 (Checksum:9a26b1) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file i2c.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 640 unrouted;       REAL time: 2 secs 

Phase 2: 597 unrouted;       REAL time: 3 secs 

Phase 3: 186 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       clock_BUFGP          |  Global  |   43   |  0.205     |  0.755      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 245


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.785
   The MAXIMUM PIN DELAY IS:                               7.912
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.337

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
         178         268         131          22          41           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file i2c.ncd.


PAR done.