i2c.syr

清华大学verilog hdl源码例子

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: i2c.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : i2c.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : i2c
Output Format                      : NGC
Target Device                      : xc2s200-5-pq208

---- Source Options
Top Module Name                    : i2c
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : i2c.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "i2c_clk.v"
Module <i2c_clk> compiled
Compiling source file "i2c_st.v"
Module <i2c_st> compiled
Compiling source file "i2c.v"
Module <i2c> compiled
No errors in compilation
Analysis of file <i2c.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <i2c>.
Module <i2c> is correct for synthesis.
 
Analyzing module <i2c_clk>.
WARNING:Xst:916 - i2c_clk.v line 77: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_clk.v line 79: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_clk.v line 85: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_clk.v line 87: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_clk.v line 89: Delay is ignored for synthesis.
Module <i2c_clk> is correct for synthesis.
 
Analyzing module <i2c_st>.
WARNING:Xst:916 - i2c_st.v line 96: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_st.v line 102: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_st.v line 105: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_st.v line 108: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_st.v line 111: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <i2c_st> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <i> in unit <i2c_st> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <i2c_st>.
    Related source file is i2c_st.v.
WARNING:Xst:1780 - Signal <ack_err> is never used or assigned.
WARNING:Xst:646 - Signal <i> is assigned but never used.
WARNING:Xst:646 - Signal <i2c_act> is assigned but never used.
WARNING:Xst:1780 - Signal <i2c_rdy> is never used or assigned.
    Using one-hot encoding for signal <i2c_state>.
    Found 1-bit register for signal <scl_cnt_en>.
    Found 1-bit register for signal <sda>.
    Found 1-bit register for signal <scl>.
    Found 8-bit register for signal <i2c_rdata>.
    Found 3-bit down counter for signal <bit_cntr>.
    Found 1-bit register for signal <cntr_done>.
    Found 1-bit register for signal <en_cntr>.
    Found 28-bit register for signal <i2c_state>.
    Found 1-bit register for signal <scl_en>.
    Summary:
	inferred   1 Counter(s).
	inferred  14 D-type flip-flop(s).
Unit <i2c_st> synthesized.


Synthesizing Unit <i2c_clk>.
    Related source file is i2c_clk.v.
    Found 1-bit register for signal <scl_tick>.
    Found 8-bit adder for signal <$n0003> created at line 79.
    Found 8-bit register for signal <cntr>.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <i2c_clk> synthesized.


Synthesizing Unit <i2c>.
    Related source file is i2c.v.
WARNING:Xst:647 - Input <addr> is never used.
WARNING:Xst:1780 - Signal <ack_l> is never used or assigned.
    Found 1-bit tristate buffer for signal <sda_pin>.
    Found 1-bit tristate buffer for signal <scl_pin>.
    Summary:
	inferred   2 Tristate(s).
Unit <i2c> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 8-bit adder                       : 1
# Counters                         : 1
 3-bit down counter                : 1
# Registers                        : 17
 8-bit register                    : 1
 1-bit register                    : 15
 28-bit register                   : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <i2c_state_25> (without init value) is constant in block <i2c_st>.

Optimizing unit <i2c> ...

Optimizing unit <i2c_clk> ...

Optimizing unit <i2c_st> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c, actual ratio is 3.
FlipFlop U3_scl_tick has been replicated 1 time(s)
FlipFlop U4_scl has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : i2c.ngr
Top Level Output File Name         : i2c
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# Registers                        : 45
#      1-bit register              : 43
#      3-bit register              : 1
#      8-bit register              : 1
# Tristates                        : 2
#      1-bit tristate buffer       : 2
# Adders/Subtractors               : 1
#      8-bit adder                 : 1

Cell Usage :
# BELS                             : 177
#      GND                         : 1
#      LUT1                        : 11
#      LUT2                        : 23
#      LUT2_D                      : 3
#      LUT3                        : 28
#      LUT3_L                      : 1
#      LUT4                        : 41
#      LUT4_D                      : 5
#      LUT4_L                      : 47
#      MUXCY                       : 7
#      MUXF5                       : 2
#      VCC                         : 1
#      XORCY                       : 7
# FlipFlops/Latches                : 55
#      FDC                         : 39
#      FDCE                        : 5
#      FDP                         : 2
#      FDPE                        : 9
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 1
#      IOBUF                       : 1
#      OBUF                        : 8
#      OBUFT                       : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      86  out of   2352     3%  
 Number of Slice Flip Flops:            55  out of   4704     1%  
 Number of 4 input LUTs:               159  out of   4704     3%  
 Number of bonded IOBs:                 11  out of    144     7%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 55    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.987ns (Maximum Frequency: 91.017MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 9.415ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clock'
Delay:               10.987ns (Levels of Logic = 4)
  Source:            U4_i2c_state_18 (FF)
  Destination:       U4_i2c_state_1 (FF)
  Source Clock:      clock rising
  Destination Clock: clock rising

  Data Path: U4_i2c_state_18 to U4_i2c_state_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              8   1.292   2.050  U4_i2c_state_18 (U4_i2c_state_18)
     LUT2:I0->O            2   0.653   1.340  U4_Ker6942_SW0 (N21348)
     LUT4:I1->O            2   0.653   1.340  U4_Ker67161 (U4_N6718)
     LUT3:I1->O            4   0.653   1.600  U4_Ker69151 (U4_N6917)
     LUT3_L:I2->LO         1   0.653   0.000  U4__n0009<1>1 (U4__n0009<1>)
     FDC:D                     0.753          U4_i2c_state_1
    ----------------------------------------
    Total                     10.987ns (4.657ns logic, 6.330ns route)
                                       (42.4% logic, 57.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
Offset:              9.415ns (Levels of Logic = 1)
  Source:            U4_scl_1 (FF)
  Destination:       scl_pin (PAD)
  Source Clock:      clock rising

  Data Path: U4_scl_1 to scl_pin
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q            12   1.292   2.400  U4_scl_1 (U4_scl_1)
     OBUFT:T->O                5.723          scl_pin_OBUFT (scl_pin)
    ----------------------------------------
    Total                      9.415ns (7.015ns logic, 2.400ns route)
                                       (74.5% logic, 25.5% route)

=========================================================================
CPU : 8.23 / 9.89 s | Elapsed : 8.00 / 10.00 s
 
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Total memory usage is 71236 kilobytes