counter16_top.cmd_log

清华大学verilog hdl源码例子

xst -intstyle ise -ifn __projnav/counter16_top.xst -ofn counter16_top.syr
ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\counter16\ise\counter16_top.v/_ngo -i  -p xc2s200-pq208-6 counter16_top.ngc counter16_top.ngd
ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\counter16\ise\counter16_top.v/_ngo -uc counter16_top.ucf  -p xc2s200-pq208-6 counter16_top.ngc counter16_top.ngd
map -intstyle ise -p xc2s200-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o counter16_top_map.ncd counter16_top.ngd counter16_top.pcf
par -w -intstyle ise -ol std -t 1 counter16_top_map.ncd counter16_top.ncd counter16_top.pcf
trce -intstyle ise -e 3 -l 3 -xml counter16_top counter16_top.ncd -o counter16_top.twr counter16_top.pcf
bitgen -intstyle ise -f counter16_top.ut counter16_top.ncd