counter16_top.twr

来自「清华大学verilog hdl源码例子」· TWR 代码 · 共 41 行

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml counter16_top
counter16_top.ncd -o counter16_top.twr counter16_top.pcf


Design file:              counter16_top.ncd
Physical constraint file: counter16_top.pcf
Device,speed:             xc2s200,-6 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |         |         |         |    2.596|
---------------+---------+---------+---------+---------+

Analysis completed Fri Feb 24 02:33:53 2006
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Peak Memory Usage: 49 MB