counter16_top.ucf

来自「清华大学verilog hdl源码例子」· UCF 代码 · 共 14 行

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "BZ"  LOC = "p205"  ;
NET "CLK"  LOC = "p80"  ;
NET "L5"  LOC = "p33"  ;
NET "S1"  LOC = "p163"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE