counter16_top.npl

来自「清华大学verilog hdl源码例子」· NPL 代码 · 共 29 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT counter16_top
DESIGN counter16_top
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE counter16.v
SOURCE counter16_top.v
DEPASSOC counter16_top counter16_top.ucf
[STATUS-ALL]
counter16_top.bitgenGroup=OK,0
counter16_top.ngcFile=WARNINGS,1140719478
[STRATEGY-LIST]
Normal=True