counter16_top.lfp

清华大学verilog hdl源码例子

# begin LFP file f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\counter16\ise\counter16_top.v\counter16_top.lfp
designfile counter16_top.ngd
INST "counter16_top" COLOR=15  ;