counter16_top.par

清华大学verilog hdl源码例子

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

TOMWANG::  Fri Feb 24 02:33:49 2006


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 counter16_top_map.ncd
counter16_top.ncd counter16_top.pcf 


Constraints file: counter16_top.pcf

Loading device database for application Par from file "counter16_top_map.ncd".
   "counter16_top" is an NCD, version 2.38, device xc2s200, package pq208, speed
-6
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <L5> must be placed at site P33.
Resolved that IOB <S1> must be placed at site P163.
Resolved that IOB <BZ> must be placed at site P205.
Resolved that GCLKIOB <CLK> must be placed at site P80.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             3 out of 140     2%
      Number of LOCed External IOBs    3 out of 3     100%

   Number of SLICEs                   16 out of 2352    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896d3) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9d1ec0) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file counter16_top.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 51 unrouted;       REAL time: 0 secs 

Phase 2: 50 unrouted;       REAL time: 0 secs 

Phase 3: 3 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |    1   |  0.000     |  0.533      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<8>    |   Local  |    3   |  0.000     |  0.765      |
+----------------------------+----------+--------+------------+-------------+
| counter16_clk16_out<10>    |   Local  |    2   |  0.000     |  1.054      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<9>    |   Local  |    2   |  0.000     |  0.985      |
+----------------------------+----------+--------+------------+-------------+
| counter16_clk16_out<11>    |   Local  |    2   |  0.000     |  0.856      |
+----------------------------+----------+--------+------------+-------------+
| counter16_clk16_out<12>    |   Local  |    2   |  0.000     |  0.832      |
+----------------------------+----------+--------+------------+-------------+
| counter16_clk16_out<13>    |   Local  |    2   |  0.000     |  0.726      |
+----------------------------+----------+--------+------------+-------------+
| counter16_clk16_out<14>    |   Local  |    2   |  0.000     |  0.728      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<0>    |   Local  |    2   |  0.000     |  0.715      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<1>    |   Local  |    2   |  0.000     |  0.853      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<2>    |   Local  |    2   |  0.000     |  0.715      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<3>    |   Local  |    2   |  0.000     |  0.887      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<4>    |   Local  |    2   |  0.000     |  0.752      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<5>    |   Local  |    2   |  0.000     |  0.856      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<6>    |   Local  |    2   |  0.000     |  1.436      |
+----------------------------+----------+--------+------------+-------------+
|  counter16_clk16_out<7>    |   Local  |    2   |  0.000     |  0.860      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 202


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.732
   The MAXIMUM PIN DELAY IS:                               3.989
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.440

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          31           2           1          17           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file counter16_top.ncd.


PAR done.