_primary.vhd

来自「清华大学verilog hdl源码例子」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity counter16 is
    port(
        reset_n         : in     vl_logic;
        clk_in          : in     vl_logic;
        clk16_out       : out    vl_logic_vector(15 downto 0)
    );
end counter16;