_info

清华大学verilog hdl源码例子

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cModel Technology
dC:\Modeltech_eval_5.6\examples
vcounter16
I2VobOadNW0So9QYh]M;Fi0
VY:Z0ajjXIC;K;VA;9zZ8`0
dC:\eden\examples\counter16\modelsim
w1020085428
FC:/eden/examples/counter16/rtl/counter16.v
L0 9
OE;L;5.6;17
r1
31
o-work work
vtb_counter16
I^eR3Dj:VTJY]QMLMbf0A]3
Vk7R6:o2c=J8_Lh0]6BP7X3
dC:\eden\examples\counter16\modelsim
w1020173594
FC:/eden/examples/counter16/rtl/tb_counter16.v
L0 5
OE;L;5.6;17
r1
31
o-work work