decoder.npl

清华大学verilog hdl源码例子

JDF G
// Created by Project Navigator ver 1.0
PROJECT decoder
DESIGN decoder
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE decoder.v
DEPASSOC decoder decoder.ucf
[STATUS-ALL]
decoder.bitgenGroup=OK,0
[STRATEGY-LIST]
Normal=True