decoder.ucf

清华大学verilog hdl源码例子

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "IN<0>"  LOC = "P163"  ;
NET "IN<1>"  LOC = "P161"  ;
NET "IN<2>"  LOC = "P109"  ;
NET "OUT<0>"  LOC = "P33"  ;
NET "OUT<1>"  LOC = "P30"  ;
NET "OUT<2>"  LOC = "P27"  ;
NET "OUT<3>"  LOC = "P23"  ;
NET "OUT<4>"  LOC = "P21"  ;
NET "OUT<5>"  LOC = "P18"  ;
NET "OUT<6>"  LOC = "P16"  ;
NET "OUT<7>"  LOC = "P14"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE