adder.ucf

来自「清华大学verilog hdl源码例子」· UCF 代码 · 共 23 行

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "A<0>"  LOC = "p163"  ;
NET "A<1>"  LOC = "p161"  ;
NET "A<2>"  LOC = "p109"  ;
NET "A<3>"  LOC = "p111"  ;
NET "B<0>"  LOC = "p113"  ;
NET "B<1>"  LOC = "p115"  ;
NET "B<2>"  LOC = "p120"  ;
NET "B<3>"  LOC = "p122"  ;
NET "SUM<0>"  LOC = "p33"  ;
NET "SUM<1>"  LOC = "p30"  ;
NET "SUM<2>"  LOC = "p27"  ;
NET "SUM<3>"  LOC = "p23"  ;
NET "SUM<4>"  LOC = "p21"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE