adder.cmd_log

清华大学verilog hdl源码例子

xst -intstyle ise -ifn __projnav/adder.xst -ofn adder.syr
ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\adder\ise\adder/_ngo -i  -p xc2s200-pq208-6 adder.ngc adder.ngd
ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\adder\ise\adder/_ngo -uc adder.ucf  -p xc2s200-pq208-6 adder.ngc adder.ngd
map -intstyle ise -p xc2s200-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o adder_map.ncd adder.ngd adder.pcf
par -w -intstyle ise -ol std -t 1 adder_map.ncd adder.ncd adder.pcf
trce -intstyle ise -e 3 -l 3 -xml adder adder.ncd -o adder.twr adder.pcf
bitgen -intstyle ise -f adder.ut adder.ncd