adder.par

清华大学verilog hdl源码例子

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

TOMWANG::  Fri Feb 24 02:12:34 2006


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 adder_map.ncd adder.ncd
adder.pcf 


Constraints file: adder.pcf

Loading device database for application Par from file "adder_map.ncd".
   "adder" is an NCD, version 2.38, device xc2s200, package pq208, speed -6
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <A<0>> must be placed at site P163.
Resolved that IOB <A<1>> must be placed at site P161.
Resolved that IOB <A<2>> must be placed at site P109.
Resolved that IOB <A<3>> must be placed at site P111.
Resolved that IOB <B<0>> must be placed at site P113.
Resolved that IOB <B<1>> must be placed at site P115.
Resolved that IOB <B<2>> must be placed at site P120.
Resolved that IOB <B<3>> must be placed at site P122.
Resolved that IOB <SUM<0>> must be placed at site P33.
Resolved that IOB <SUM<1>> must be placed at site P30.
Resolved that IOB <SUM<2>> must be placed at site P27.
Resolved that IOB <SUM<3>> must be placed at site P23.
Resolved that IOB <SUM<4>> must be placed at site P21.


Device utilization summary:

   Number of External IOBs            13 out of 140     9%
      Number of LOCed External IOBs   13 out of 13    100%

   Number of SLICEs                    2 out of 2352    1%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98969b) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:995bf5) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file adder.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 14 unrouted;       REAL time: 2 secs 

Phase 2: 14 unrouted;       REAL time: 2 secs 

Phase 3: 1 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 284


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.267
   The MAXIMUM PIN DELAY IS:                               4.728
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.854

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           2           5           1           4           2           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file adder.ncd.


PAR done.