_primary.vhd

来自「清华大学verilog hdl源码例子」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity adder is
    port(
        a               : in     vl_logic_vector(3 downto 0);
        b               : in     vl_logic_vector(3 downto 0);
        sum             : out    vl_logic_vector(4 downto 0)
    );
end adder;