_primary.vhd

来自「清华大学verilog hdl源码例子」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity comparator is
    port(
        a               : in     vl_logic_vector(3 downto 0);
        b               : in     vl_logic_vector(3 downto 0);
        y0              : out    vl_logic;
        y1              : out    vl_logic;
        y2              : out    vl_logic
    );
end comparator;