fpga_40rs232.twr

清华大学verilog hdl源码例子

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml fpga_40RS232
fpga_40RS232.ncd -o fpga_40RS232.twr fpga_40RS232.pcf


Design file:              fpga_40RS232.ncd
Physical constraint file: fpga_40RS232.pcf
Device,speed:             xc2s200,-5 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |         |         |         |    3.885|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
CTS            |RTS            |    8.291|
reset1         |segout<0>      |   17.294|
reset1         |segout<1>      |   17.080|
reset1         |segout<2>      |   17.093|
reset1         |segout<3>      |   17.272|
reset1         |segout<4>      |   17.100|
reset1         |segout<5>      |   17.473|
reset1         |segout<6>      |   16.644|
reset1         |segout<7>      |   17.585|
---------------+---------------+---------+

Analysis completed Sun Feb 26 16:53:32 2006
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Peak Memory Usage: 47 MB