📄 fpga_40rs232.bld

📁 清华大学verilog hdl源码例子

💻 BLD

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Release 6.2i - ngdbuild G.28Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -intstyle ise -dd
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\rs232\ise\rs23240x/_ngo
-uc fpga_40XRS232.ucf -p xc2s200-pq208-5 fpga_40RS232.ngc fpga_40RS232.ngd Reading NGO file
"f:/trainsilicon/fpgaschool/testcade/fpga40xc200/basic2/rs232/ise/rs23240x/fpga_
40RS232.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "fpga_40XRS232.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Total memory usage is 38076 kilobytesWriting NGD file "fpga_40RS232.ngd" ...Writing NGDBUILD log file "fpga_40RS232.bld"...

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