fpga_40rs232.syr

清华大学verilog hdl源码例子

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: fpga_40RS232.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : fpga_40RS232.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : fpga_40RS232
Output Format                      : NGC
Target Device                      : xc2s200-5-pq208

---- Source Options
Top Module Name                    : fpga_40RS232
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fpga_40RS232.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "serial.v"
Module <serial> compiled
Compiling source file "diag.v"
Module <diag> compiled
Compiling source file "fpga_40XRS232.v"
Module <fpga_40RS232> compiled
No errors in compilation
Analysis of file <fpga_40RS232.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <fpga_40RS232>.
Module <fpga_40RS232> is correct for synthesis.
 
Analyzing module <serial>.
Module <serial> is correct for synthesis.
 
Analyzing module <diag>.
Module <diag> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <diag>.
    Related source file is diag.v.
WARNING:Xst:647 - Input <int_tx> is never used.
    Found 8-bit tristate buffer for signal <int_data_out>.
    Found 1-bit register for signal <int_rd>.
    Found 1-bit register for signal <int_wr>.
    Found 1-bit register for signal <int_rd_q>.
    Found 8-bit register for signal <rx_data>.
    Summary:
	inferred  11 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <diag> synthesized.


Synthesizing Unit <serial>.
    Related source file is serial.v.
    Found 8-bit tristate buffer for signal <data_out>.
    Found 1-bit register for signal <tx>.
    Found 1-bit register for signal <int_rx>.
    Found 1-bit register for signal <int_tx>.
    Found 4-bit comparator less for signal <$n0011> created at line 76.
    Found 1-bit register for signal <cts_q>.
    Found 1-bit register for signal <rd_q>.
    Found 9-bit register for signal <rx_buffer>.
    Found 1-bit register for signal <rx_q>.
    Found 8-bit register for signal <rx_reg>.
    Found 8-bit up counter for signal <sync_count>.
    Found 4-bit up counter for signal <tx_bit>.
    Found 9-bit register for signal <tx_buffer>.
    Found 8-bit up counter for signal <tx_count>.
    Found 9 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   3 Counter(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   9 Multiplexer(s).
	inferred   8 Tristate(s).
Unit <serial> synthesized.


Synthesizing Unit <fpga_40RS232>.
    Related source file is fpga_40XRS232.v.
    Found 3-bit up counter for signal <div>.
    Summary:
	inferred   1 Counter(s).
Unit <fpga_40RS232> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 4
 8-bit up counter                  : 2
 3-bit up counter                  : 1
 4-bit up counter                  : 1
# Registers                        : 13
 8-bit register                    : 2
 9-bit register                    : 2
 1-bit register                    : 9
# Comparators                      : 1
 4-bit comparator less             : 1
# Multiplexers                     : 1
 9-bit 2-to-1 multiplexer          : 1
# Tristates                        : 2
 8-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <int_tx> is unconnected in block <serial>.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <fpga_40RS232> ...

Optimizing unit <diag> ...

Optimizing unit <serial> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <serial_int_tx> is unconnected in block <fpga_40RS232>.
Building and optimizing final netlist ...
Register serial_rd_q equivalent to diag_int_rd_q has been removed
Found area constraint ratio of 100 (+ 5) on block fpga_40RS232, actual ratio is 2.