rs23240x.npl

来自「清华大学verilog hdl源码例子」· NPL 代码 · 共 29 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT rs23240x
DESIGN rs23240x
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE diag.v
SOURCE fpga_40XRS232.v
SOURCE serial.v
DEPASSOC fpga_40RS232 fpga_40XRS232.ucf
[STATUS-ALL]
fpga_40RS232.bitgenGroup=OK,0
[STRATEGY-LIST]
Normal=True