fpga_40rs232.pcf

清华大学verilog hdl源码例子

SCHEMATIC START ;
// created by map version G.28 on Sun Feb 26 16:53:27 2006 
COMP "reset1" LOCATE =  SITE "P163" LEVEL 1; 
COMP "CTS" LOCATE =  SITE "P127" LEVEL 1; 
COMP "RD" LOCATE =  SITE "P134" LEVEL 1; 
COMP "TD" LOCATE =  SITE "P132" LEVEL 1; 
COMP "segout<0>" LOCATE =  SITE "P33" LEVEL 1; 
COMP "segout<1>" LOCATE =  SITE "P30" LEVEL 1; 
COMP "segout<2>" LOCATE =  SITE "P27" LEVEL 1; 
COMP "segout<3>" LOCATE =  SITE "P23" LEVEL 1; 
COMP "segout<4>" LOCATE =  SITE "P21" LEVEL 1; 
COMP "segout<5>" LOCATE =  SITE "P18" LEVEL 1; 
COMP "segout<6>" LOCATE =  SITE "P16" LEVEL 1; 
COMP "segout<7>" LOCATE =  SITE "P14" LEVEL 1; 
COMP "RTS" LOCATE =  SITE "P125" LEVEL 1; 
COMP "CLK" LOCATE =  SITE "P80" LEVEL 1; 
SCHEMATIC END ;