fpga_40rs232.par

清华大学verilog hdl源码例子

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

TOMWANG::  Sun Feb 26 16:53:28 2006


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 fpga_40RS232_map.ncd
fpga_40RS232.ncd fpga_40RS232.pcf 


Constraints file: fpga_40RS232.pcf

Loading device database for application Par from file "fpga_40RS232_map.ncd".
   "fpga_40RS232" is an NCD, version 2.38, device xc2s200, package pq208, speed
-5
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <reset1> must be placed at site P163.
Resolved that IOB <CTS> must be placed at site P127.
Resolved that IOB <RD> must be placed at site P134.
Resolved that IOB <TD> must be placed at site P132.
Resolved that IOB <segout<0>> must be placed at site P33.
Resolved that IOB <segout<1>> must be placed at site P30.
Resolved that IOB <segout<2>> must be placed at site P27.
Resolved that IOB <segout<3>> must be placed at site P23.
Resolved that IOB <segout<4>> must be placed at site P21.
Resolved that IOB <segout<5>> must be placed at site P18.
Resolved that IOB <segout<6>> must be placed at site P16.
Resolved that IOB <segout<7>> must be placed at site P14.
Resolved that IOB <RTS> must be placed at site P125.
Resolved that GCLKIOB <CLK> must be placed at site P80.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            13 out of 140     9%
      Number of LOCed External IOBs   13 out of 13    100%

   Number of SLICEs                   51 out of 2352    2%

   Number of GCLKs                     1 out of 4      25%
   Number of TBUFs                    16 out of 2464    1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899a9) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:99f6a5) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file fpga_40RS232.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 345 unrouted;       REAL time: 0 secs 

Phase 2: 321 unrouted;       REAL time: 0 secs 

Phase 3: 55 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |    2   |  0.000     |  0.668      |
+----------------------------+----------+--------+------------+-------------+
|              CLK1          |   Local  |   36   |  1.556     |  3.744      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 282


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.141
   The MAXIMUM PIN DELAY IS:                               8.002
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.416

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 9.00  d >= 9.00
   ---------   ---------   ---------   ---------   ---------   ---------
         204         110          15          15           1           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file fpga_40RS232.ncd.


PAR done.