fpga_40xrs232.ucf

清华大学verilog hdl源码例子

#PACE: Start of Constraints extracted by PACE from the Design
NET "CLK" LOC = "P80";
NET "RD" LOC = "P134";
NET "TD" LOC = "P132";
NET "RTS" LOC = "P125";
NET "CTS" LOC = "P127";
NET "reset1" LOC = "P163";
NET "segout<0>" LOC = "P33";
NET "segout<1>" LOC = "P30";
NET "segout<2>" LOC = "P27";
NET "segout<3>" LOC = "P23";
NET "segout<4>" LOC = "P21";
NET "segout<5>" LOC = "P18";
NET "segout<6>" LOC = "P16";
NET "segout<7>" LOC = "P14";