prev_cmp_topclock.tan.qmsg

VHDL写的数字钟

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "hour1:u3\|Enhour " "Info: Detected ripple clock \"hour1:u3\|Enhour\" as buffer" {  } { { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 9 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "hour1:u3\|Enhour" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "minute1:u2\|Enmin " "Info: Detected ripple clock \"minute1:u2\|Enmin\" as buffer" {  } { { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 9 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "minute1:u2\|Enmin" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "second1:u1\|Ensec " "Info: Detected ripple clock \"second1:u1\|Ensec\" as buffer" {  } { { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 9 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "second1:u1\|Ensec" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register minute1:u2\|min\[4\] register minute1:u2\|min\[4\] 199.28 MHz 5.018 ns Internal " "Info: Clock \"clk\" has Internal fmax of 199.28 MHz between source register \"minute1:u2\|min\[4\]\" and destination register \"minute1:u2\|min\[4\]\" (period= 5.018 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.757 ns + Longest register register " "Info: + Longest register to register delay is 4.757 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute1:u2\|min\[4\] 1 REG LC_X19_Y12_N8 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y12_N8; Fanout = 5; REG Node = 'minute1:u2\|min\[4\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { minute1:u2|min[4] } "NODE_NAME" } } { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.442 ns) 1.764 ns minute1:u2\|Equal0~70 2 COMB LC_X15_Y12_N4 5 " "Info: 2: + IC(1.322 ns) + CELL(0.442 ns) = 1.764 ns; Loc. = LC_X15_Y12_N4; Fanout = 5; COMB Node = 'minute1:u2\|Equal0~70'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.764 ns" { minute1:u2|min[4] minute1:u2|Equal0~70 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.590 ns) 3.596 ns minute1:u2\|min~180 3 COMB LC_X19_Y12_N9 1 " "Info: 3: + IC(1.242 ns) + CELL(0.590 ns) = 3.596 ns; Loc. = LC_X19_Y12_N9; Fanout = 1; COMB Node = 'minute1:u2\|min~180'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.832 ns" { minute1:u2|Equal0~70 minute1:u2|min~180 } "NODE_NAME" } } { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.738 ns) 4.757 ns minute1:u2\|min\[4\] 4 REG LC_X19_Y12_N8 5 " "Info: 4: + IC(0.423 ns) + CELL(0.738 ns) = 4.757 ns; Loc. = LC_X19_Y12_N8; Fanout = 5; REG Node = 'minute1:u2\|min\[4\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.161 ns" { minute1:u2|min~180 minute1:u2|min[4] } "NODE_NAME" } } { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.770 ns ( 37.21 % ) " "Info: Total cell delay = 1.770 ns ( 37.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.987 ns ( 62.79 % ) " "Info: Total interconnect delay = 2.987 ns ( 62.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.757 ns" { minute1:u2|min[4] minute1:u2|Equal0~70 minute1:u2|min~180 minute1:u2|min[4] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "4.757 ns" { minute1:u2|min[4] {} minute1:u2|Equal0~70 {} minute1:u2|min~180 {} minute1:u2|min[4] {} } { 0.000ns 1.322ns 1.242ns 0.423ns } { 0.000ns 0.442ns 0.590ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.208 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.561 ns) + CELL(0.935 ns) 7.965 ns second1:u1\|Ensec 2 REG LC_X8_Y10_N1 9 " "Info: 2: + IC(5.561 ns) + CELL(0.935 ns) = 7.965 ns; Loc. = LC_X8_Y10_N1; Fanout = 9; REG Node = 'second1:u1\|Ensec'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.496 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.532 ns) + CELL(0.711 ns) 12.208 ns minute1:u2\|min\[4\] 3 REG LC_X19_Y12_N8 5 " "Info: 3: + IC(3.532 ns) + CELL(0.711 ns) = 12.208 ns; Loc. = LC_X19_Y12_N8; Fanout = 5; REG Node = 'minute1:u2\|min\[4\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.243 ns" { second1:u1|Ensec minute1:u2|min[4] } "NODE_NAME" } } { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 25.52 % ) " "Info: Total cell delay = 3.115 ns ( 25.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.093 ns ( 74.48 % ) " "Info: Total interconnect delay = 9.093 ns ( 74.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.208 ns" { clk second1:u1|Ensec minute1:u2|min[4] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.208 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|min[4] {} } { 0.000ns 0.000ns 5.561ns 3.532ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.208 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.561 ns) + CELL(0.935 ns) 7.965 ns second1:u1\|Ensec 2 REG LC_X8_Y10_N1 9 " "Info: 2: + IC(5.561 ns) + CELL(0.935 ns) = 7.965 ns; Loc. = LC_X8_Y10_N1; Fanout = 9; REG Node = 'second1:u1\|Ensec'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.496 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.532 ns) + CELL(0.711 ns) 12.208 ns minute1:u2\|min\[4\] 3 REG LC_X19_Y12_N8 5 " "Info: 3: + IC(3.532 ns) + CELL(0.711 ns) = 12.208 ns; Loc. = LC_X19_Y12_N8; Fanout = 5; REG Node = 'minute1:u2\|min\[4\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.243 ns" { second1:u1|Ensec minute1:u2|min[4] } "NODE_NAME" } } { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 25.52 % ) " "Info: Total cell delay = 3.115 ns ( 25.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.093 ns ( 74.48 % ) " "Info: Total interconnect delay = 9.093 ns ( 74.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.208 ns" { clk second1:u1|Ensec minute1:u2|min[4] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.208 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|min[4] {} } { 0.000ns 0.000ns 5.561ns 3.532ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.208 ns" { clk second1:u1|Ensec minute1:u2|min[4] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.208 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|min[4] {} } { 0.000ns 0.000ns 5.561ns 3.532ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.208 ns" { clk second1:u1|Ensec minute1:u2|min[4] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.208 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|min[4] {} } { 0.000ns 0.000ns 5.561ns 3.532ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.757 ns" { minute1:u2|min[4] minute1:u2|Equal0~70 minute1:u2|min~180 minute1:u2|min[4] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "4.757 ns" { minute1:u2|min[4] {} minute1:u2|Equal0~70 {} minute1:u2|min~180 {} minute1:u2|min[4] {} } { 0.000ns 1.322ns 1.242ns 0.423ns } { 0.000ns 0.442ns 0.590ns 0.738ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.208 ns" { clk second1:u1|Ensec minute1:u2|min[4] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.208 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|min[4] {} } { 0.000ns 0.000ns 5.561ns 3.532ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.208 ns" { clk second1:u1|Ensec minute1:u2|min[4] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.208 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|min[4] {} } { 0.000ns 0.000ns 5.561ns 3.532ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "second1:u1\|Ensec set clk 1.606 ns register " "Info: tsu for register \"second1:u1\|Ensec\" (data pin = \"set\", clock pin = \"clk\") is 1.606 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.310 ns + Longest pin register " "Info: + Longest pin to register delay is 9.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns set 1 PIN PIN_21 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_21; Fanout = 2; PIN Node = 'set'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { set } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.194 ns) + CELL(0.292 ns) 7.955 ns hour1:u3\|Enhour~12 2 COMB LC_X8_Y10_N6 3 " "Info: 2: + IC(6.194 ns) + CELL(0.292 ns) = 7.955 ns; Loc. = LC_X8_Y10_N6; Fanout = 3; COMB Node = 'hour1:u3\|Enhour~12'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.486 ns" { set hour1:u3|Enhour~12 } "NODE_NAME" } } { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.867 ns) 9.310 ns second1:u1\|Ensec 3 REG LC_X8_Y10_N1 9 " "Info: 3: + IC(0.488 ns) + CELL(0.867 ns) = 9.310 ns; Loc. = LC_X8_Y10_N1; Fanout = 9; REG Node = 'second1:u1\|Ensec'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.355 ns" { hour1:u3|Enhour~12 second1:u1|Ensec } "NODE_NAME" } } { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.628 ns ( 28.23 % ) " "Info: Total cell delay = 2.628 ns ( 28.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.682 ns ( 71.77 % ) " "Info: Total interconnect delay = 6.682 ns ( 71.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.310 ns" { set hour1:u3|Enhour~12 second1:u1|Ensec } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "9.310 ns" { set {} set~out0 {} hour1:u3|Enhour~12 {} second1:u1|Ensec {} } { 0.000ns 0.000ns 6.194ns 0.488ns } { 0.000ns 1.469ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.741 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.741 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.561 ns) + CELL(0.711 ns) 7.741 ns second1:u1\|Ensec 2 REG LC_X8_Y10_N1 9 " "Info: 2: + IC(5.561 ns) + CELL(0.711 ns) = 7.741 ns; Loc. = LC_X8_Y10_N1; Fanout = 9; REG Node = 'second1:u1\|Ensec'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.272 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.16 % ) " "Info: Total cell delay = 2.180 ns ( 28.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.561 ns ( 71.84 % ) " "Info: Total interconnect delay = 5.561 ns ( 71.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.741 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "7.741 ns" { clk {} clk~out0 {} second1:u1|Ensec {} } { 0.000ns 0.000ns 5.561ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.310 ns" { set hour1:u3|Enhour~12 second1:u1|Ensec } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "9.310 ns" { set {} set~out0 {} hour1:u3|Enhour~12 {} second1:u1|Ensec {} } { 0.000ns 0.000ns 6.194ns 0.488ns } { 0.000ns 1.469ns 0.292ns 0.867ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.741 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "7.741 ns" { clk {} clk~out0 {} second1:u1|Ensec {} } { 0.000ns 0.000ns 5.561ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Day\[1\] day1:u4\|day\[1\] 27.335 ns register " "Info: tco from clock \"clk\" to destination pin \"Day\[1\]\" through register \"day1:u4\|day\[1\]\" is 27.335 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 23.401 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 23.401 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.561 ns) + CELL(0.935 ns) 7.965 ns second1:u1\|Ensec 2 REG LC_X8_Y10_N1 9 " "Info: 2: + IC(5.561 ns) + CELL(0.935 ns) = 7.965 ns; Loc. = LC_X8_Y10_N1; Fanout = 9; REG Node = 'second1:u1\|Ensec'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.496 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.512 ns) + CELL(0.935 ns) 12.412 ns minute1:u2\|Enmin 3 REG LC_X15_Y12_N5 9 " "Info: 3: + IC(3.512 ns) + CELL(0.935 ns) = 12.412 ns; Loc. = LC_X15_Y12_N5; Fanout = 9; REG Node = 'minute1:u2\|Enmin'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.447 ns" { second1:u1|Ensec minute1:u2|Enmin } "NODE_NAME" } } { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.701 ns) + CELL(0.935 ns) 18.048 ns hour1:u3\|Enhour 4 REG LC_X15_Y14_N9 3 " "Info: 4: + IC(4.701 ns) + CELL(0.935 ns) = 18.048 ns; Loc. = LC_X15_Y14_N9; Fanout = 3; REG Node = 'hour1:u3\|Enhour'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.636 ns" { minute1:u2|Enmin hour1:u3|Enhour } "NODE_NAME" } } { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.642 ns) + CELL(0.711 ns) 23.401 ns day1:u4\|day\[1\] 5 REG LC_X1_Y6_N2 4 " "Info: 5: + IC(4.642 ns) + CELL(0.711 ns) = 23.401 ns; Loc. = LC_X1_Y6_N2; Fanout = 4; REG Node = 'day1:u4\|day\[1\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.353 ns" { hour1:u3|Enhour day1:u4|day[1] } "NODE_NAME" } } { "day1.vhd" "" { Text "I:/topclock/day1.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.985 ns ( 21.30 % ) " "Info: Total cell delay = 4.985 ns ( 21.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.416 ns ( 78.70 % ) " "Info: Total interconnect delay = 18.416 ns ( 78.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "23.401 ns" { clk second1:u1|Ensec minute1:u2|Enmin hour1:u3|Enhour day1:u4|day[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "23.401 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|Enmin {} hour1:u3|Enhour {} day1:u4|day[1] {} } { 0.000ns 0.000ns 5.561ns 3.512ns 4.701ns 4.642ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "day1.vhd" "" { Text "I:/topclock/day1.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.710 ns + Longest register pin " "Info: + Longest register to pin delay is 3.710 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns day1:u4\|day\[1\] 1 REG LC_X1_Y6_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y6_N2; Fanout = 4; REG Node = 'day1:u4\|day\[1\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { day1:u4|day[1] } "NODE_NAME" } } { "day1.vhd" "" { Text "I:/topclock/day1.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.586 ns) + CELL(2.124 ns) 3.710 ns Day\[1\] 2 PIN PIN_55 0 " "Info: 2: + IC(1.586 ns) + CELL(2.124 ns) = 3.710 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'Day\[1\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.710 ns" { day1:u4|day[1] Day[1] } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 57.25 % ) " "Info: Total cell delay = 2.124 ns ( 57.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.586 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.586 ns ( 42.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.710 ns" { day1:u4|day[1] Day[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.710 ns" { day1:u4|day[1] {} Day[1] {} } { 0.000ns 1.586ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "23.401 ns" { clk second1:u1|Ensec minute1:u2|Enmin hour1:u3|Enhour day1:u4|day[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "23.401 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|Enmin {} hour1:u3|Enhour {} day1:u4|day[1] {} } { 0.000ns 0.000ns 5.561ns 3.512ns 4.701ns 4.642ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.710 ns" { day1:u4|day[1] Day[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.710 ns" { day1:u4|day[1] {} Day[1] {} } { 0.000ns 1.586ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}