topclock.fit.qmsg

VHDL写的数字钟

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.196 ns register register " "Info: Estimated most critical path is register to register delay of 4.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute1:u2\|min\[0\] 1 REG LAB_X12_Y7 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y7; Fanout = 10; REG Node = 'minute1:u2\|min\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { minute1:u2|min[0] } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.698 ns) + CELL(0.575 ns) 1.273 ns minute1:u2\|Add1~132COUT1_134 2 COMB LAB_X13_Y7 2 " "Info: 2: + IC(0.698 ns) + CELL(0.575 ns) = 1.273 ns; Loc. = LAB_X13_Y7; Fanout = 2; COMB Node = 'minute1:u2\|Add1~132COUT1_134'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.273 ns" { minute1:u2|min[0] minute1:u2|Add1~132COUT1_134 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.353 ns minute1:u2\|Add1~124COUT1_135 3 COMB LAB_X13_Y7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.353 ns; Loc. = LAB_X13_Y7; Fanout = 2; COMB Node = 'minute1:u2\|Add1~124COUT1_135'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { minute1:u2|Add1~132COUT1_134 minute1:u2|Add1~124COUT1_135 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.433 ns minute1:u2\|Add1~118COUT1_136 4 COMB LAB_X13_Y7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.433 ns; Loc. = LAB_X13_Y7; Fanout = 2; COMB Node = 'minute1:u2\|Add1~118COUT1_136'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { minute1:u2|Add1~124COUT1_135 minute1:u2|Add1~118COUT1_136 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.513 ns minute1:u2\|Add1~126COUT1 5 COMB LAB_X13_Y7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.513 ns; Loc. = LAB_X13_Y7; Fanout = 2; COMB Node = 'minute1:u2\|Add1~126COUT1'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { minute1:u2|Add1~118COUT1_136 minute1:u2|Add1~126COUT1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.771 ns minute1:u2\|Add1~128 6 COMB LAB_X13_Y7 3 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.771 ns; Loc. = LAB_X13_Y7; Fanout = 3; COMB Node = 'minute1:u2\|Add1~128'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { minute1:u2|Add1~126COUT1 minute1:u2|Add1~128 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.450 ns minute1:u2\|Add1~129 7 COMB LAB_X13_Y7 1 " "Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 2.450 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'minute1:u2\|Add1~129'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { minute1:u2|Add1~128 minute1:u2|Add1~129 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.590 ns) 3.342 ns minute1:u2\|min~181 8 COMB LAB_X14_Y7 1 " "Info: 8: + IC(0.302 ns) + CELL(0.590 ns) = 3.342 ns; Loc. = LAB_X14_Y7; Fanout = 1; COMB Node = 'minute1:u2\|min~181'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.892 ns" { minute1:u2|Add1~129 minute1:u2|min~181 } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.738 ns) 4.196 ns minute1:u2\|min\[5\] 9 REG LAB_X14_Y7 6 " "Info: 9: + IC(0.116 ns) + CELL(0.738 ns) = 4.196 ns; Loc. = LAB_X14_Y7; Fanout = 6; REG Node = 'minute1:u2\|min\[5\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.854 ns" { minute1:u2|min~181 minute1:u2|min[5] } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.080 ns ( 73.40 % ) " "Info: Total cell delay = 3.080 ns ( 73.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.116 ns ( 26.60 % ) " "Info: Total interconnect delay = 1.116 ns ( 26.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.196 ns" { minute1:u2|min[0] minute1:u2|Add1~132COUT1_134 minute1:u2|Add1~124COUT1_135 minute1:u2|Add1~118COUT1_136 minute1:u2|Add1~126COUT1 minute1:u2|Add1~128 minute1:u2|Add1~129 minute1:u2|min~181 minute1:u2|min[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y11 x23_y21 " "Info: The peak interconnect region extends from location x12_y11 to location x23_y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 07 07:01:25 2008 " "Info: Processing ended: Mon Apr 07 07:01:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/topclock.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/topclock.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}