📄 topclock.flow.rpt
字号:
Flow report for topclock
Mon Apr 07 07:01:30 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+------------------------------------------+
; Flow Status ; Successful - Mon Apr 07 07:01:30 2008 ;
; Quartus II Version ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name ; topclock ;
; Top-level Entity Name ; topclock ;
; Family ; Cyclone ;
; Device ; EP1C6Q240C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 110 / 5,980 ( 2 % ) ;
; Total pins ; 34 / 185 ( 18 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 92,160 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/07/2008 07:01:17 ;
; Main task ; Compilation ;
; Revision Name ; topclock ;
+-------------------+---------------------+
+----------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-----------------+--------+---------------+-------------+-------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-----------------+--------+---------------+-------------+-------------+
; LL_MEMBER_STATE ; Locked ; -- ; -- ; Root Region ;
; LL_ROOT_REGION ; On ; -- ; -- ; Root Region ;
+-----------------+--------+---------------+-------------+-------------+
+-------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+
; Module Name ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:02 ;
; Fitter ; 00:00:04 ;
; Assembler ; 00:00:02 ;
; Timing Analyzer ; 00:00:01 ;
; Total ; 00:00:09 ;
+----------------------+--------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off topclock -c topclock
quartus_fit --read_settings_files=off --write_settings_files=off topclock -c topclock
quartus_asm --read_settings_files=off --write_settings_files=off topclock -c topclock
quartus_tan --read_settings_files=off --write_settings_files=off topclock -c topclock --timing_analysis_only
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -