📄 topclock.sim.rpt
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+--------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 60.96 % ;
; Total nodes checked ; 609 ;
; Total output ports checked ; 648 ;
; Total output ports with complete 1/0-value coverage ; 395 ;
; Total output ports with no 1/0-value coverage ; 231 ;
; Total output ports with no 1-value coverage ; 241 ;
; Total output ports with no 0-value coverage ; 243 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+-------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------------+
; |topclock|clk ; |topclock|clk ; out ;
; |topclock|set ; |topclock|set ; out ;
; |topclock|setm ; |topclock|setm ; out ;
; |topclock|seth ; |topclock|seth ; out ;
; |topclock|setd ; |topclock|setd ; out ;
; |topclock|Sec[0] ; |topclock|Sec[0] ; pin_out ;
; |topclock|Sec[1] ; |topclock|Sec[1] ; pin_out ;
; |topclock|Sec[2] ; |topclock|Sec[2] ; pin_out ;
; |topclock|Sec[3] ; |topclock|Sec[3] ; pin_out ;
; |topclock|Sec[4] ; |topclock|Sec[4] ; pin_out ;
; |topclock|Sec[5] ; |topclock|Sec[5] ; pin_out ;
; |topclock|min[0] ; |topclock|min[0] ; pin_out ;
; |topclock|min[1] ; |topclock|min[1] ; pin_out ;
; |topclock|min[2] ; |topclock|min[2] ; pin_out ;
; |topclock|min[3] ; |topclock|min[3] ; pin_out ;
; |topclock|min[4] ; |topclock|min[4] ; pin_out ;
; |topclock|hour[0] ; |topclock|hour[0] ; pin_out ;
; |topclock|hour[1] ; |topclock|hour[1] ; pin_out ;
; |topclock|hour[2] ; |topclock|hour[2] ; pin_out ;
; |topclock|hour[3] ; |topclock|hour[3] ; pin_out ;
; |topclock|Day[0] ; |topclock|Day[0] ; pin_out ;
; |topclock|Day[1] ; |topclock|Day[1] ; pin_out ;
; |topclock|Day[2] ; |topclock|Day[2] ; pin_out ;
; |topclock|day1:u4|day[0] ; |topclock|day1:u4|day[0] ; out ;
; |topclock|day1:u4|d~0 ; |topclock|day1:u4|d~0 ; out ;
; |topclock|day1:u4|d~1 ; |topclock|day1:u4|d~1 ; out ;
; |topclock|day1:u4|d~2 ; |topclock|day1:u4|d~2 ; out ;
; |topclock|day1:u4|day~0 ; |topclock|day1:u4|day~0 ; out ;
; |topclock|day1:u4|day~1 ; |topclock|day1:u4|day~1 ; out ;
; |topclock|day1:u4|day~2 ; |topclock|day1:u4|day~2 ; out ;
; |topclock|day1:u4|day[1] ; |topclock|day1:u4|day[1] ; out ;
; |topclock|day1:u4|day[2] ; |topclock|day1:u4|day[2] ; out ;
; |topclock|day1:u4|comb~0 ; |topclock|day1:u4|comb~0 ; out0 ;
; |topclock|day1:u4|comb~1 ; |topclock|day1:u4|comb~1 ; out ;
; |topclock|day1:u4|comb~2 ; |topclock|day1:u4|comb~2 ; out ;
; |topclock|day1:u4|comb~3 ; |topclock|day1:u4|comb~3 ; out ;
; |topclock|day1:u4|d[0] ; |topclock|day1:u4|d[0] ; out ;
; |topclock|day1:u4|d[1] ; |topclock|day1:u4|d[1] ; out ;
; |topclock|day1:u4|d[2] ; |topclock|day1:u4|d[2] ; out ;
; |topclock|day1:u4|comb~7 ; |topclock|day1:u4|comb~7 ; out0 ;
; |topclock|day1:u4|comb~8 ; |topclock|day1:u4|comb~8 ; out0 ;
; |topclock|day1:u4|comb~9 ; |topclock|day1:u4|comb~9 ; out0 ;
; |topclock|hour1:u3|h~2 ; |topclock|hour1:u3|h~2 ; out ;
; |topclock|hour1:u3|h~3 ; |topclock|hour1:u3|h~3 ; out ;
; |topclock|hour1:u3|h~4 ; |topclock|hour1:u3|h~4 ; out ;
; |topclock|hour1:u3|h~5 ; |topclock|hour1:u3|h~5 ; out ;
; |topclock|hour1:u3|h~6 ; |topclock|hour1:u3|h~6 ; out ;
; |topclock|hour1:u3|h~7 ; |topclock|hour1:u3|h~7 ; out ;
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