counter.vhd

用层次化设计完成倒计时装置 输入：16位二进制倒计时起始数字、倒计时起始数字的输入使能信号、 倒计时开始信号、复位信号、1MHz时钟信号、10Hz时钟信号。 输出：数码管数据信号及宣统信号

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity counter is
port(
	clk: in std_logic;
	clk10: in std_logic;
	number: in std_logic_vector (15 downto 0);
	s_state: in std_logic_vector (1 downto 0);
	data: inout std_logic_vector (15 downto 0);
	s_over: out std_logic
	);
end counter;

architecture behaver of counter is
begin
	process (clk,clk10,s_state)
	begin
		if clk'event and clk='1' then
			case s_state is
				when "00" => 
					data<=number;
					s_over<='0';
				when "01"=>
					if clk10'event and clk10='1' then
						if data>"0000000000000000" then
							data<=data-'1';
							s_over<='0';
						else
--							data<="0000000000000000";	-- not necessary
							s_over<='1';
						end if;
					end if;
				when "11" =>
					data<="0000000000000000";
					s_over<='1';
				when others =>
					data<="0000000000000000";
					s_over<='0';
			end case;
		end if;
	end process;
end behaver;