d11.vhd

来自「用层次化设计完成倒计时装置 输入：16位二进制倒计时起始数字、倒计时起始数字的」· VHDL 代码 · 共 74 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity d11 is
port(
	clk,clk10: in std_logic;					-- 1MHz, 10Hz
	reset: in std_logic;						-- RESET	SW1
	start: in std_logic;						-- START	SW2
	keyl: in std_logic_vector (3 downto 0);		-- keyboard's line
	keyc: in std_logic_vector (3 downto 0);		-- keyboard's lie
	remember: in std_logic;						-- decide to record the input
	sel: out std_logic_vector (5 downto 0);		-- select signal
	leds: out std_logic_vector (7 downto 0);	-- 8_leds
	over: out std_logic
	);
end d11;

architecture behaver of d11 is

	component display is		-- submodule of display
	port(
		clk: in std_logic;
		data: in std_logic_vector (15 downto 0);
		s_over: in std_logic;
		sel: out std_logic_vector (5 downto 0);
		leds: out std_logic_vector (7 downto 0);
		over: out std_logic
		);
	end component;
	component counter is		-- submodule of counter
	port(
		clk: in std_logic;
		clk10: in std_logic;
		number: in std_logic_vector (15 downto 0);
		s_state: in std_logic_vector (1 downto 0);
		data: inout std_logic_vector (15 downto 0);
		s_over: out std_logic
		);
	end component;
	component control is		-- submodule os control
	port(
		clk: in std_logic;
		reset: in std_logic;
		start: in std_logic;
		s_over: in std_logic;
		s_state: out std_logic_vector (1 downto 0)
		);
	end component;

	component input is			-- input the start number
	port(
		clk: in std_logic;
		reset: in std_logic;
		keyl: in std_logic_vector (3 downto 0);
		keyc: in std_logic_vector (3 downto 0);
		remember: in std_logic;
		number: out std_logic_vector (15 downto 0)
		);	
	end component;
	
	signal number: std_logic_vector (15 downto 0);
	signal data: std_logic_vector (15 downto 0);
	signal s_over: std_logic;							-- mission completed
	signal s_state: std_logic_vector (1 downto 0);
	
begin
	u0: display port map (clk,data,s_over,sel,leds,over);
	u1: counter port map (clk,clk10,number,s_state,data,s_over);
	u2: control port map (clk,reset,start,s_over,s_state);
	u3: input port map (clk,reset,keyl,keyc,remember,number);
end behaver;