input.vhd

来自「用层次化设计完成倒计时装置 输入：16位二进制倒计时起始数字、倒计时起始数字的」· VHDL 代码 · 共 76 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity input is
port(
	clk: in std_logic;
	reset: in std_logic;
	keyl: in std_logic_vector (3 downto 0);
	keyc: in std_logic_vector (3 downto 0);
	remember: in std_logic;			-- 
	number: out std_logic_vector (15 downto 0)
	);
end input;

architecture behaver of input is
	signal tempnumber: std_logic_vector (15 downto 0);
begin
	process (clk,reset,keyl,keyc,remember)
	begin
		if clk'event and clk='1' then
			if reset='0' then
				number<="0000000000000000";
			elsif remember='0' then
				tempnumber<="0000000000000000";
			elsif remember='1' then
				if keyl(0)'event and keyl(0)='1' then
					if keyc(0)='1' then
						number(0)<='1';
					elsif keyc(1)='1' then
						number(1)<='1';
					elsif keyc(2)='1' then
						number(2)<='1';
					elsif keyc(3)='1' then
						number(3)<='1';
					end if;
				end if;
				if keyl(1)'event and keyl(1)='1' then
					if keyc(0)='1' then
						number(4)<='1';
					elsif keyc(1)='1' then
						number(5)<='1';
					elsif keyc(2)='1' then
						number(6)<='1';
					elsif keyc(3)='1' then
						number(7)<='1';
					end if;
				end if;
				if keyl(2)'event and keyl(2)='1' then
					if keyc(0)='1' then
						number(8)<='1';
					elsif keyc(1)='1' then
						number(9)<='1';
					elsif keyc(2)='1' then
						number(10)<='1';
					elsif keyc(3)='1' then
						number(11)<='1';
					end if;
				end if;
				if keyl(3)'event and keyl(3)='1' then
					if keyc(0)='1' then
						number(12)<='1';
					elsif keyc(1)='1' then
						number(13)<='1';
					elsif keyc(2)='1' then
						number(14)<='1';
					elsif keyc(3)='1' then
						number(15)<='1';
					end if;
				end if;
			end if;
		end if;
	end process;
end behaver;