📄 light.sim.rpt
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+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 60.43 % ;
; Total nodes checked ; 230 ;
; Total output ports checked ; 230 ;
; Total output ports with complete 1/0-value coverage ; 139 ;
; Total output ports with no 1/0-value coverage ; 91 ;
; Total output ports with no 1-value coverage ; 91 ;
; Total output ports with no 0-value coverage ; 91 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+--------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------+
; |controller|numa~6 ; |controller|numa~6 ; out ;
; |controller|numa~7 ; |controller|numa~7 ; out ;
; |controller|numa~8 ; |controller|numa~8 ; out ;
; |controller|numa~9 ; |controller|numa~9 ; out ;
; |controller|numa~10 ; |controller|numa~10 ; out ;
; |controller|numa~11 ; |controller|numa~11 ; out ;
; |controller|numa~12 ; |controller|numa~12 ; out ;
; |controller|numa~13 ; |controller|numa~13 ; out ;
; |controller|numa~14 ; |controller|numa~14 ; out ;
; |controller|numa~15 ; |controller|numa~15 ; out ;
; |controller|greena~0 ; |controller|greena~0 ; out ;
; |controller|yellowa~0 ; |controller|yellowa~0 ; out ;
; |controller|reda~0 ; |controller|reda~0 ; out ;
; |controller|greena~1 ; |controller|greena~1 ; out ;
; |controller|yellowa~1 ; |controller|yellowa~1 ; out ;
; |controller|numa~16 ; |controller|numa~16 ; out ;
; |controller|numa~17 ; |controller|numa~17 ; out ;
; |controller|numa~18 ; |controller|numa~18 ; out ;
; |controller|numa~19 ; |controller|numa~19 ; out ;
; |controller|numa~20 ; |controller|numa~20 ; out ;
; |controller|greena~reg0 ; |controller|greena~reg0 ; out ;
; |controller|yellowa~reg0 ; |controller|yellowa~reg0 ; out ;
; |controller|numa[4]~reg0 ; |controller|numa[4]~reg0 ; out ;
; |controller|numa[3]~reg0 ; |controller|numa[3]~reg0 ; out ;
; |controller|numa[2]~reg0 ; |controller|numa[2]~reg0 ; out ;
; |controller|numa[1]~reg0 ; |controller|numa[1]~reg0 ; out ;
; |controller|numa[0]~reg0 ; |controller|numa[0]~reg0 ; out ;
; |controller|reda~reg0 ; |controller|reda~reg0 ; out ;
; |controller|clock ; |controller|clock ; out ;
; |controller|countnum[0] ; |controller|countnum[0] ; out ;
; |controller|countnum[1] ; |controller|countnum[1] ; out ;
; |controller|countnum[2] ; |controller|countnum[2] ; out ;
; |controller|countnum[3] ; |controller|countnum[3] ; out ;
; |controller|countnum[4] ; |controller|countnum[4] ; out ;
; |controller|countnum[5] ; |controller|countnum[5] ; out ;
; |controller|numa[0] ; |controller|numa[0] ; pin_out ;
; |controller|numa[1] ; |controller|numa[1] ; pin_out ;
; |controller|numa[2] ; |controller|numa[2] ; pin_out ;
; |controller|numa[3] ; |controller|numa[3] ; pin_out ;
; |controller|numa[4] ; |controller|numa[4] ; pin_out ;
; |controller|reda ; |controller|reda ; pin_out ;
; |controller|greena ; |controller|greena ; pin_out ;
; |controller|yellowa ; |controller|yellowa ; pin_out ;
; |controller|LessThan~50 ; |controller|LessThan~50 ; out0 ;
; |controller|LessThan~51 ; |controller|LessThan~51 ; out0 ;
; |controller|LessThan~52 ; |controller|LessThan~52 ; out0 ;
; |controller|LessThan~53 ; |controller|LessThan~53 ; out0 ;
; |controller|LessThan~54 ; |controller|LessThan~54 ; out0 ;
; |controller|LessThan~55 ; |controller|LessThan~55 ; out0 ;
; |controller|LessThan~56 ; |controller|LessThan~56 ; out0 ;
; |controller|LessThan~57 ; |controller|LessThan~57 ; out0 ;
; |controller|LessThan~58 ; |controller|LessThan~58 ; out0 ;
; |controller|LessThan~59 ; |controller|LessThan~59 ; out0 ;
; |controller|LessThan~60 ; |controller|LessThan~60 ; out0 ;
; |controller|LessThan~61 ; |controller|LessThan~61 ; out0 ;
; |controller|LessThan~62 ; |controller|LessThan~62 ; out0 ;
; |controller|LessThan~63 ; |controller|LessThan~63 ; out0 ;
; |controller|LessThan~64 ; |controller|LessThan~64 ; out0 ;
; |controller|lpm_add_sub:add_rtl_2|addcore:adder|addcore:adder[0]|ps[1]~1 ; |controller|lpm_add_sub:add_rtl_2|addcore:adder|addcore:adder[0]|ps[1]~1 ; out0 ;
; |controller|lpm_add_sub:add_rtl_2|addcore:adder|addcore:adder[0]|psi[1] ; |controller|lpm_add_sub:add_rtl_2|addcore:adder|addcore:adder[0]|psi[1] ; out0 ;
; |controller|lpm_add_sub:add_rtl_2|addcore:adder|addcore:adder[0]|gn[2] ; |controller|lpm_add_sub:add_rtl_2|addcore:adder|addcore:adder[0]|gn[2] ; out0 ;
; |controller|lpm_add_sub:add_rtl_2|addcore:adder|addcore:adder[0]|ps[3]~3 ; |controller|lpm_add_sub:add_rtl_2|addcore:adder|addcore:adder[0]|ps[3]~3 ; out0 ;
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